參數(shù)資料
型號(hào)： LH7A404
廠商： Sharp Corporation
英文描述： 32 BIT SYSTEM ON CHIP
中文描述： 32位片上系統(tǒng)
文件頁(yè)數(shù)： 24/51頁(yè)
文件大小： 387K
代理商： LH7A404
LH7A404
32-Bit System-on-Chip
24
Advance Data Sheet
Embedded SRAM
The LH7A404 incorporates 80KB of embedded
SRAM. This embedded memory is used for storing
code, data, or LCD frame data and is contiguous with
external SDRAM. The 80KB is large enough to store a
QVGA panel (320 × 240) at 8 bits per pixel, equivalent
to 70KB of information.
Locating the frame buffer on chip reduces the overall
power consumed by any application that uses the
LH7A404. Normally, the system performs external
accesses to acquire this data. The LCD controller auto-
matically uses an overflow frame buffer in SDRAM if a
larger screen size is required. This overflow buffer can
be located on any 4KB page boundary in SDRAM,
allowing software to set the MMU (in the LCD control-
ler) page tables such that the two memory areas
appear contiguous. Byte, half-word and word accesses
are permissible.
Static Memory Controller (SMC)
The asynchronous Static Memory Controller (SMC)
provides an interface between the AMBA AHB system
bus and external (off-chip) memory devices.
The SMC simultaneously supports up to eight inde-
pendently configurable memory banks. Each memory
bank can support:
SRAM
ROM
Flash EPROM
Burst ROM memory.
Each memory bank may use devices using either 8-,
16-, or 32-bit external memory data paths. The memory
controller can be configured to support either little-
endian or big-endian operation.
The memory banks can be configured to support:
Non-burst read and write accesses only to high-
speed CMOS static RAM
Non-burst write accesses, nonburst read accesses
and asynchronous page mode read accesses to
fast-boot block flash memory.
The SMC has six main functions:
Memory bank select
Access sequencing
Wait state generation
Byte lane write control
External bus interface
Compact Flash or PCMCIA interfacing.
SDRAM (Synchronous) Memory Controller
The SDRAM (Synchronous) Memory Controller pro-
vides a high speed memory interface to a wide variety
of synchronous memory devices, including Synchro-
nous DRAM, Synchronous Flash and Synchronous
ROMs.
The key features of the controller are:
LCD DMA port for high bandwidth
Up to four Synchronous Memory banks can be inde-
pendently set up
Includes special configuration bits for Synchronous
ROM operation
Includes ability to program Synchronous Flash
devices using write and erase commands
On booting from Synchronous ROM, (and optionally
with Synchronous Flash), a configuration sequence is
performed before releasing the processor from reset
Data is transferred between the controller and the
Synchronous DRAM in four-word bursts. Longer
transfers within the same page are concatenated,
forming a seamless burst
Programmable for 16- or 32-bit data bus size
Two reset domains enable Synchronous DRAM con-
tents to be preserved over a ‘soft’ reset
Power saving Synchronous Memory SCKE and
external clock modes provided.
Secure Digital/MultiMediaCard (MMC)
The SD Memory Card (Secure Digital Memory Card)
is a flash-based memory card that meets the security,
capacity, performance, and environment requirements
inherent in electronic devices. The SD Memory Card
host supports MultiMediaCard (MMC) operation as well
and is forward compatible. The main difference
between SD Card and MMC is the initialization process.
The Secure Digital and MMC adapter can be used as
an MMC card or as an SD card and supports the full
MMC/SD bus protocol as defined in the MMC system
specification 2.11 provided by the MMC Definition
Group and the SD Memory Card Spec v1.0 from the SD
group. The controller can also implement the SPI inter-
face to the cards.
SD/MMC INTERFACE DESCRIPTION
The SD/MMC controller uses the three-wire serial
data bus (clock, command, and data) to input and out-
put data to and from the MMC card, and to configure
and acquire status information from the card’s regis-
ters. The SD differs only in that it has four data lines.
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