參數(shù)資料
型號: LH7A404
廠商: Sharp Corporation
英文描述: 32 BIT SYSTEM ON CHIP
中文描述: 32位片上系統(tǒng)
文件頁數(shù): 37/51頁
文件大?。?/td> 387K
代理商: LH7A404
32-Bit System-on-Chip
LH7A404
Advance Data Sheet
37
Synchronous Memory Controller Waveforms
Figure 10 shows the waveform and timing for a Syn-
chronous Burst Read (page already open). Figure 11
shows the waveform and timing for synchronous mem-
ory to activate a bank and Write.
Figure 10. Synchronous Burst Read
Figure 11. Synchronous Bank Activate and Write
t
SCLK
LH7A404-13
SA[13:0],
SBANK[1:0]
D[31:0]
NOTES:
1. SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCSx.
2. tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC.
3. tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC.
4. nDQM is static LOW.
5. SDCKE is static HIGH.
SCLK
SDRAMcmd
t
OVXXX
t
OVB
t
OHXXX
READ
BANK,
COLUMN
tOVA
tISD tIHD
DATA n
DATA n + 1
DATA n + 2
DATA n + 3
LH7A404-14
D[31:0]
SCLK
SDCKE
SDRAMcmd
tSCLK
tOVC0
tOVXXX
tOVA
tOHXXX
tOVA
NOTES:
1. SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCSx.
2. tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC. Refer to the AC timing table.
3. tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC.
4. nDQM is static LOW.
ACTIVE
WRITE
DATA
BANK,
ROW
BANK,
COLUMN
tOVD
tOHD
SA[13:0],
SBANK[1:0]
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