參數(shù)資料
型號(hào): LM2743
廠商: National Semiconductor Corporation
英文描述: N-Channel FET Synchronous Buck Regulator Controller for Conversion from 3.3V
中文描述: N溝道場效應(yīng)管同步降壓穩(wěn)壓控制器,用于從3.3V轉(zhuǎn)換
文件頁數(shù): 10/23頁
文件大?。?/td> 653K
代理商: LM2743
Application Information
(Continued)
NORMAL OPERATION
While in normal operation mode, the LM2743 regulates the
output voltage by controlling the duty cycle of the high side
and low side FETs.
The equation governing output voltage is:
The PWM frequency is adjustable between 50kHz and
2MHz and is set by an external resistor, R
, between the
FREQ pin and ground. The resistance needed for a desired
frequency is approximately:
where a
= 0.206375, a
= 3.691525, a
= (-0.076875) are
the coefficients, F
OSC
is the frequency in Hz, and R
FADJ
is
the resistance in k
.
SS/TRACK
When the LM2743 is used for sequencing purposes, some
care has to be taken. Once the shutdown voltage goes
above V
, a 17μApull-up current is activated as shown
in
Figure 2
. This current is used to create an internal hyster-
esis (170mV); however, high external impedances will affect
the SD pin level as well. The external impedance must be
lower than 10k
to work properly without glitching the qui-
escent current of the chip. In that scenario the SS current will
turn on and off during the glitching or most likely no switching
will occur at all, due to the SS voltage being very low.
The LM2743 is also adequate for tracking purposes through
the SS/TRACK pin. The tracking circuit, in the design ex-
amples below, contains a Master Power Supply with V
OUT1
=
5V and an LM2743 with V
OUT2
=1.8V.
Three cases are described:
1.
Both output voltages, V
and V
, rise together,
reaching their final values at the same time,
2.
Both output voltages rise together at the same rate until
V
OUT2
= 1.8V, and finally
3.
Output voltage V
OUT2
starts rising 3.24ms after V
OUT1
starts.
The calculation of the feedback resistors
Figure 3
for all
cases is based on the Tracking Equation. Since V
=0.6V,
V
OUT2
=1.8V, and R
FB2
=10k
, then the R
FB1
becomes 5k
.
Case 1: Rise together
Both, V
and V
, start rising, and reach their nominal
values at the same time as shown in
Figure 4
. This means
that V
OUT2
rises at slower rate then V
OUT1
.
V
SS
= V
OUT1
*(R
3
/(R
3
+R
4
))
20095204
FIGURE 1. Start-Up Behavior
20095206
FIGURE 2. SD Pin Logic
20095207
FIGURE 3. Block Diagram of Case 1
L
www.national.com
10
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