參數(shù)資料
型號: LM2743
廠商: National Semiconductor Corporation
英文描述: N-Channel FET Synchronous Buck Regulator Controller for Conversion from 3.3V
中文描述: N溝道場效應(yīng)管同步降壓穩(wěn)壓控制器,用于從3.3V轉(zhuǎn)換
文件頁數(shù): 12/23頁
文件大?。?/td> 653K
代理商: LM2743
Application Information
(Continued)
If the tracking through SS/TRACK pin is not used, a capaci-
tor to ground is needed to limit the inrush current.
MOSFET GATE DRIVERS
The LM2743 has two gate drivers designed for driving
N-channel MOSFETs in a synchronous mode. Power for the
drivers is supplied through the BOOT pin. For the high side
gate (HG), to fully turn the top FET on, the BOOT voltage
must be at least one V
greater than V
(V
2V +
V
). This voltage can be supplied from a separate voltage
source or from a local charge pump structure, the bootstrap.
A charge pump can be built using a diodes and small ca-
pacitors, as shown in the below figures. The capacitor
serves to maintain enough voltage between the top FET
gate and source to control the device even when the top FET
is on and its source has risen up to the input voltage level.
The LM2743 gate drives use a BiCMOS design. Unlike some
other bipolar control ICs, the gate drivers have rail-to-rail
swing, ensuring no spurious turn-on due to capacitive cou-
pling.
The LM2743 can operate its internal circuitry at the V
range from 3.0V to 6.0V. However, the external FETs may
operate more efficiently with higher gate drive voltage.
Fig-
ure 9
shows a typical bootstrap method where the voltage
applied to the FETs is V
CC
- V
D
.
This means that if V
is 3.0V, the gate drive for the FETs is
approximately 2.5V. This voltage could be too low to fully
turn the FET on. As a result I
2
R losses could be higher than
expected.
In the next bootstrap configuration (
Figure 10
) the voltage
applied to the high side FET is V
CC
- 2V
D
and to the low side
FET is
V
CC
- 2V
D
+ V
IN
.
If V
and V
are both 3.0V, then 5V is developed at BOOT
pin and the low side FET can be driven fully on. The high
side FET however may have difficulty turning on since the
applied gate drive is only 2V in this case.
The
Figure 11
shows next example of bootstrap configura-
tion. In this case the low gate drive voltage on the top FET is
resolved. Now the gate drive on both, the low and high, side
FETs is
V
CC
- 3V
D
+ V
IN
.
20095211
FIGURE 8. Timing Behavior of Case 3
20095212
FIGURE 9. Bootstrap Configuration 1
20095213
FIGURE 10. Bootstrap Configuration 2
L
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