參數(shù)資料
型號: LM2743
廠商: National Semiconductor Corporation
英文描述: N-Channel FET Synchronous Buck Regulator Controller for Conversion from 3.3V
中文描述: N溝道場效應管同步降壓穩(wěn)壓控制器,用于從3.3V轉換
文件頁數(shù): 2/23頁
文件大?。?/td> 653K
代理商: LM2743
Connection Diagram
20095202
14-Lead Plastic TSSOP
θ
JA
= 155C/W
NS Package Number MTC14
Pin Description
BOOT (Pin 1)
- Supply rail for the N-channel MOSFET gate
drive. The voltage should be at least one gate threshold
(V
) above the regulator input voltage (V
IN
) to properly
turn on the high-side FET.
LG (Pin 2)
- Gate drive for the low-side N-channel MOSFET.
This signal is interlocked with HG (Pin 14) to avoid a shoot-
through problem.
PGND (Pins 3, 13)
- Ground for low-side FET drive circuitry.
Connect to system ground.
SGND (Pin 4)
- Ground for signal level circuitry. Connect to
system ground.
V
CC
(Pin 5)
Supply rail for the controller.
PWGD (Pin 6)
- Power good pin. This is an open drain
output. The pin is pulled low when the chip is in under-
voltage flag (UVF), over-voltage flag (OVF), or UVLO mode.
During normal operation, this pin is connected to V
CC
or
other low voltage source through a pull-up resistor (R
PULL-
UP
).
I
(Pin 7)
- Current limit threshold setting. This sources a
fixed 40μA current. A resistor of appropriate value should be
connected between this pin and the drain of the low-side
FET.
EAO (Pin 8)
- Output of the error amplifier. The voltage level
on this pin is compared with an internally generated ramp
signal to determine the duty cycle. This pin is necessary for
compensating the control loop.
SS (Pin 9)
- Soft start and track pin. A 10 μA current is
sourced from this pin. This pin is connected to the non-
inverting input of the error amplifier during soft start, or any
time the voltage is below the reference. To track power
supplies connect a resistor divider (smaller than 10k
for
better precision) from the output of the master supply directly
to the SS pin. To limit the inrush current of a single power
supply, place a capacitor to ground (see Application
Information/Start Up for appropriate capacitance value). This
pin should not be forced before SD or V
CC
(above the
UVLO).
FB (Pin 10)
- This is the inverting input of the error amplifier,
which is used for sensing the output voltage and compen-
sating the control loop. The FB current is negligible.
FREQ (Pin 11)
- The switching frequency (F
) is set by
connecting a resistor (R
FADJ
) between this pin and ground.
SD (Pin 12)
- IC shutdown pin. To assure proper IC start-up
the SD pin should not be left floating. When this pin is pulled
low the chip turns both, high and low, sides off. While this pin
is low, the IC will not start up. This pin features a precision
threshold for power supply sequencing, as well as a lower
threshold to ensure minimal quiescent current.
HG (Pin 14)
- Gate drive for the high-side N-channel MOS-
FET. This signal is interlocked with LG (Pin 2) to avoid a
shoot-through problem.
L
www.national.com
2
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