參數(shù)資料
型號: LMX2335
廠商: National Semiconductor Corporation
英文描述: PLLatinum Dual Frequency Synthesizer for RF Personal Communications(PLLatinum技術(shù)用于射頻個(gè)人通訊的雙通道頻率合成器)
中文描述: PLLatinum雙頻率合成射頻個(gè)人通信(PLLatinum技術(shù)用于射頻個(gè)人通訊的雙通道頻率合成器)
文件頁數(shù): 8/17頁
文件大小: 392K
代理商: LMX2335
Functional Description
The simplified block diagram below shows the 22-bit data register, two 15-bit R Counters and two 18-bit N Counters (intermediate
latches are not shown). The data stream is clocked (on the rising edge of Clock) into the DATAregister, MSB first. The data stored
in the shift register is loaded into one of the 4 appropriate latches on the rising edge of LE. The last two bits are the Control Bits.
The DATA is transferred into the counters as follows:
Control Bits
C1
0
0
1
1
DATA Location
C2
0
1
0
1
RF2 R Counter
RF1 R Counter
RF2 N Counter
RF1 N Counter
PROGRAMMABLE REFERENCE DIVIDERS (RF1 AND RF2 R COUNTERS)
If the Control Bits are 00 or 01 (00 for RF2 and 01 for RF1) data is transferred from the 22-bit shift register into a latch which sets
the 15-bit R Counter. Serial data format is shown below.
15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)
Divide
Ratio
3
4
32767
R
15
0
0
R
14
0
0
R
13
0
0
R
12
0
0
R
11
0
0
R
10
0
0
R
9
0
0
1
R
8
0
0
1
R
7
0
0
1
R
6
0
0
1
R
5
0
0
1
R
4
0
0
1
R
3
0
1
1
R
2
1
0
1
R
1
1
0
1
1
1
1
1
1
1
Notes:
Divide ratios less than 3 are prohibited.
Divide ratio: 3 to 32767
R1 to R15: These bits select the divide ratio of the programmable reference divider.
Data is shifted in MSB first.
DS012332-1
DS012332-4
L
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