參數(shù)資料
型號: LP61L256B
廠商: AMIC Technology Corporation
英文描述: 32K X 8 Bit High SPEED LOW VCC CMOS SRAM
中文描述: 32K的× 8位高速CMOS SRAM的低虛擬通道連接
文件頁數(shù): 5/11頁
文件大?。?/td> 132K
代理商: LP61L256B
LP61L256B Series
(August, 2001, Version 1.0)
5
AMIC Technology, Inc.
AC Characteristics (continued)
LP61L256B-12
Symbol
Parameter
Min.
Max.
Unit
Write Cycle
t
WC
Write Cycle Time
12
-
ns
t
CW
Chip Enable to End of Write
10
-
ns
t
AS
Address Setup Time of Write
0
-
ns
t
AW
Address Valid to End of Write
10
-
ns
t
WP
Write Pulse Width
8
-
ns
t
WR
Write Recovery Time
0
-
ns
t
WHZ
Write to Output in High Z
0
7
ns
t
DW
Data to Write Time Overlap
8
-
ns
t
DH
Data Hold from Write Time
0
-
ns
t
OW
Output Active from End of Write
5
-
ns
Notes: t
CHZ
, t
OHZ
and t
WHZ
are defined as the time at which the outputs achieve the open circuit condition and are not
referred to output voltage levels.
Timing Waveforms
Read Cycle 1
(1, 2, 4)
t
RC
t
OH
t
AA
t
OH
Address
D
OUT
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