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參數(shù)資料
| 型號(hào)： | LP61L256B |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 32K X 8 Bit High SPEED LOW VCC CMOS SRAM |
| 中文描述： | 32K的× 8位高速CMOS SRAM的低虛擬通道連接 |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大?。?/td> | 132K |
| 代理商： | LP61L256B |
LP61L256B Series
(August, 2001, Version 1.0)
6
AMIC Technology, Inc.
Timing Waveforms (continued)
Read Cycle 2
(1, 3, 4)
t
CLZ5
t
ACE
t
CHZ5
D
OUT
CE
Read Cycle 3
(1)
t
RC
Address
D
OUT
t
AA
t
OE
t
OLZ5
t
ACE
t
CLZ5
t
CHZ5
t
OH
OE
t
OHZ5
CE
Note: 1. WE is high for Read cycle.
2. Device is continuously enabled, CE = V
IL
.
3. Address valid prior to or coincident with CE transition low.
4. OE = V
IL
.
5. Transition is measured
±
200mV from steady state. This parameter is sampled and not 100% tested.
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| LP61L256BS-12 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:32K X 8 Bit High SPEED LOW VCC CMOS SRAM |
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| LP61L256CS-12 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:32K X 8 BIT HIGH SPEED CMOS SRAM |
| LP61L256CS-15 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:32K X 8 BIT HIGH SPEED CMOS SRAM |
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