參數(shù)資料
型號: LP61L256CS-12
廠商: AMIC Technology Corporation
元件分類: SRAM
英文描述: 32K X 8 BIT HIGH SPEED CMOS SRAM
中文描述: 32K的× 8位高速CMOS SRAM的
文件頁數(shù): 5/11頁
文件大?。?/td> 110K
代理商: LP61L256CS-12
LP61L256C Series
PRELIMINARY
(November, 2001, Version 0.0)
4
AMIC Technology, Inc.
Truth Table
Mode
CE
OE
WE
I/O Operation
Supply Current
Standby
H
X
X
High Z
I
SB
, I
SB1
Output Disable
L
H
H
High Z
I
CC1
Read
L
L
H
D
OUT
I
CC1
Write
L
X
L
D
IN
I
CC1
Note: X = H or L
Capacitance
(T
A
= 25
°
C, f = 1.0MHz)
Symbol
Parameter
Min.
Max.
Unit
Conditions
C
IN
*
Input Capacitance
10
pF
V
IN
= 0V
C
I/O
*
Input/Output Capacitance
10
pF
V
I/O
= 0V
* These parameters are sampled and not 100% tested.
AC Characteristics
(T
A
= 0
°
C to +70
°
C, VCC = 3.3V
±
10%)
Symbol
Parameter
LP61L256C-12
LP61L256C-15
Unit
Min.
Max.
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
12
-
15
-
ns
t
AA
Address Access Time
-
12
-
15
ns
t
ACE
Chip Enable Access Time
-
12
-
15
ns
t
OE
Output Enable to Output Valid
-
6
-
8
ns
t
CLZ
Chip Enable to Output in Low Z
3
-
3
-
ns
t
OLZ
Output Enable to Output in Low Z
0
-
0
-
ns
t
CHZ
Chip Disable Output in High Z
0
6
-
8
ns
t
OHZ
Output Disable to Output in High Z
0
6
0
8
ns
t
OH
Output Hold from Address Change
3
-
3
-
ns
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