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參數(shù)資料
| 型號(hào)： | LP61L256CS-12 |
| 廠商： | AMIC Technology Corporation |
| 元件分類： | SRAM |
| 英文描述： | 32K X 8 BIT HIGH SPEED CMOS SRAM |
| 中文描述： | 32K的× 8位高速CMOS SRAM的 |
| 文件頁(yè)數(shù)： | 9/11頁(yè) |
| 文件大?。?/td> | 110K |
| 代理商： | LP61L256CS-12 |
LP61L256C Series
PRELIMINARY
(November, 2001, Version 0.0)
8
AMIC Technology, Inc.
AC Test Conditions
Input Pulse Levels
0V to 3.0V
Input Rise and Fall Time
2 ns
Input and Output Timing Reference Levels
1.5V
Output Load
See Figures 1 and 2
+3.3V
I/O
351
317
5pF*
* Including scope and jig.
Z
O
=50
OUTPUT
R
L
=50
V
T
=1.5V
Figure 1. Output Load
Figure 2. Output Load for t
CLZ
, t
OLZ
,
t
CHZ
, t
OHZ
, t
WHZ
, and t
OW
Data Retention Characteristics
(T
A
= 0
°
C to 70
°
C)
Symbol
Parameter
Min.
Max.
Unit
Conditions
V
DR
VCC for Data Retention
2
3.6
V
CE
≥
VCC - 0.2V
I
CCDR
Data Retention Current
-
2
mA
VCC = 2.0V
CE
≥
VCC - 0.2V
V
IN
≥
VCC - 0.2V or
V
IN
≤
0.2V
t
CDR
Chip Disable to Data Retention
Time
0
-
ns
See Retention Waveform
t
R
Operation Recovery Time
t
RC
*
-
ns
t
RC
= Read Cycle Time
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