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參數(shù)資料
| 型號： | LP61L256CS-12 |
| 廠商： | AMIC Technology Corporation |
| 元件分類： | SRAM |
| 英文描述： | 32K X 8 BIT HIGH SPEED CMOS SRAM |
| 中文描述： | 32K的× 8位高速CMOS SRAM的 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 110K |
| 代理商： | LP61L256CS-12 |
LP61L256C Series
PRELIMINARY
(November, 2001, Version 0.0)
5
AMIC Technology, Inc.
AC Characteristics (continued)
Symbol
Parameter
LP61L256C-12
LP61L256C-15
Unit
Min.
Max.
Min.
Max
Write Cycle
t
WC
Write Cycle Time
12
-
15
-
ns
t
CW
Chip Enable to End of Write
10
-
12
-
ns
t
AS
Address Setup Time of Write
0
-
0
-
ns
t
AW
Address Valid to End of Write
10
-
12
-
ns
t
WP
Write Pulse Width
10
-
12
-
ns
t
WR
Write Recovery Time
0
-
0
-
ns
t
WHZ
Write to Output in High Z
0
6
0
8
ns
t
DW
Data to Write Time Overlap
6
-
7
-
ns
t
DH
Data Hold from Write Time
0
-
0
-
ns
t
OW
Output Active from End of Write
3
-
3
-
ns
Notes: t
CHZ
, t
OHZ
and t
WHZ
are defined as the time at which the outputs achieve the open circuit condition and are not
referred to output voltage levles.
Timing Waveforms
Read Cycle 1
(1)
t
RC
Address
D
OUT
t
AA
t
OE
t
OLZ5
t
ACE
t
CLZ5
t
CHZ5
t
OH
OE
t
OHZ5
CE
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| LP61L256CS-15 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:32K X 8 BIT HIGH SPEED CMOS SRAM |
| LP-61PMBT | 制造商:Polycase 功能描述:Enclosure, Box/Lid, Desktop, ABS,UL94-5VA, Black, 5.56x3.8x1.25 In, LP Series |
| LP-61PXXT | 制造商:Polycase 功能描述:Enclosure;Box/Lid;Desktop;ABS,UL94-5VA;Black;5.56x3.8x1.25 In;LP Series |
| LP6202 | 制造商:POWER 制造商全稱:Lowpower Semiconductor inc 功能描述:Synchronous Boost DC/DC Regulator |
| LP6202A | 制造商:POWER 制造商全稱:Lowpower Semiconductor inc 功能描述:Synchronous Boost DC/DC Regulator |
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