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參數(shù)資料
| 型號： | LP61L256CS-12 |
| 廠商： | AMIC Technology Corporation |
| 元件分類： | SRAM |
| 英文描述： | 32K X 8 BIT HIGH SPEED CMOS SRAM |
| 中文描述： | 32K的× 8位高速CMOS SRAM的 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 110K |
| 代理商： | LP61L256CS-12 |
LP61L256C Series
PRELIMINARY
(November, 2001, Version 0.0)
6
AMIC Technology, Inc.
Timing Waveforms (continued)
Read Cycle 2
(1, 2, 4)
t
RC
t
OH
t
AA
t
OH
Address
D
OUT
Read Cycle 3
(1, 3, 4,)
t
CLZ5
t
ACE
t
CHZ5
D
OUT
CE
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled, CE = V
IL
.
3. Address valid prior to or coincident with CE transition low.
4. OE = V
IL
.
5. Transition is measured
±
200mV from steady state. This parameter is sampled and not 100% tested.
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| LP61L256CS-15 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:32K X 8 BIT HIGH SPEED CMOS SRAM |
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