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參數資料
| 型號： | LPC1311FHN33,551 |
| 廠商： | NXP Semiconductors |
| 文件頁數： | 29/74頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT 8KB FLASH 33HVQFN |
| 產品培訓模塊： | LPCXpresso |
| 特色產品： | LPC1300 Series Cortex-M3 MCUs |
| 標準包裝： | 260 |
| 系列： | LPC13xx |
| 核心處理器： | ARM? Cortex?-M3 |
| 芯體尺寸： | 32-位 |
| 速度： | 72MHz |
| 連通性： | I²C，Microwire，SPI，SSI，UART/USART |
| 外圍設備： | 欠壓檢測/復位，POR，WDT |
| 輸入/輸出數： | 28 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 4K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 數據轉換器： | A/D 8x10b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 33-VQFN 裸露焊盤，33-HVQFN，33-SQFN，33-DHVQFN |
| 包裝： | 托盤 |
| 配用： | 622-1005-ND - USB IN-CIRCUIT PROG ARM7 LPC2K |
| 其它名稱： | 568-4915 935289654551 |
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LPC1311_13_42_43
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 June 2012
35 of 74
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
[1]
Typical ratings are not guaranteed. The values listed are at room temperature (25
°C), nominal supply voltages.
[2]
For LPC1342 and LPC1343 only: For USB operation 3.0 V
≤ VDD ≤ 3.6 V. Guaranteed by design.
[3]
IRC enabled; system oscillator disabled; system PLL disabled.
[4]
IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled.
[5]
BOD disabled.
[6]
All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART, SSP, trace clock, and SysTick timer disabled in
the syscon block.
[7]
For LPC1342/43: USB_DP and USB_DM pulled LOW externally.
[8]
IRC disabled; system oscillator enabled; system PLL enabled.
[9]
All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 0FFF.
[10] WAKEUP pin pulled HIGH externally. An external pull-up resistor is required on the RESET pin for the Deep power-down mode.
[11] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.
[12] Including voltage on outputs in 3-state mode.
[13] VDD supply voltage must be present.
[14] 3-state outputs go into 3-state mode in Deep power-down mode.
[15] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[16] To VSS.
[17] 3.0 V
≤ VDD ≤ 3.6 V.
[18] Includes external resistors of 33
Ω± 1 % on USB_DP and USB_DM.
[1]
The ADC is monotonic, there are no missing codes.
[2]
The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 8.
VOH
HIGH-level output
voltage
driven; for low-/full-speed;
RL of 15 k
Ω to GND
[17] 2.8
-
3.5
V
Ctrans
transceiver capacitance pin to GND
[17] --20
pF
ZDRV
driver output
impedance for driver
which is not high-speed
capable
with 33
Ω series resistor; steady state
drive
[18][17] 36
-
44.1
Ω
Table 7.
Static characteristics …continued
Tamb =
40 °C to +85 °C, unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
Table 8.
ADC static characteristics
Tamb =
40 °C to +85 °C unless otherwise specified; ADC frequency 4.5 MHz, VDD = 2.5 V to 3.6 V.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIA
analog input voltage
0
-
VDD
V
Cia
analog input capacitance
-
1
pF
ED
differential linearity error
[1][2] --
±1LSB
EL(adj)
integral non-linearity
[3] --
±1.5
LSB
EO
offset error
[4] --
±3.5
LSB
EG
gain error
[5] --0.6
%
ET
absolute error
[6] --
±4LSB
Rvsi
voltage source interface
resistance
--40
k
Ω
Ri
input resistance
[7][8] --2.5
M
Ω
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