參數(shù)資料
型號: LPC1311FHN33,551
廠商: NXP Semiconductors
文件頁數(shù): 51/74頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 8KB FLASH 33HVQFN
產(chǎn)品培訓(xùn)模塊: LPCXpresso
特色產(chǎn)品: LPC1300 Series Cortex-M3 MCUs
標(biāo)準(zhǔn)包裝: 260
系列: LPC13xx
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 72MHz
連通性: I²C,Microwire,SPI,SSI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,WDT
輸入/輸出數(shù): 28
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 33-VQFN 裸露焊盤,33-HVQFN,33-SQFN,33-DHVQFN
包裝: 托盤
配用: 622-1005-ND - USB IN-CIRCUIT PROG ARM7 LPC2K
其它名稱: 568-4915
935289654551
LPC1311_13_42_43
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 June 2012
55 of 74
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
10.7 SSP0/1 interface
Remark: The SSP1 interface is available on the LPC1313FBD48/01 only.
[1]
Tcy(clk) = (SSPCLKDIV
× (1 + SCR) × CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the
main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0
register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).
[2]
Tamb =
40 °C to +85 °C.
[3]
Tcy(clk) = 12
× Tcy(PCLK).
[4]
Tamb = 25
°C; VDD = 3.3 V.
Table 19.
Dynamic characteristics: SSP pins in SPI mode
Symbol
Parameter
Conditions
Min
Max
Unit
SSP master
Tcy(clk)
clock cycle time
full-duplex mode
40
-
ns
when only transmitting [1]
27.8
-
ns
tDS
data set-up time
in SPI mode;
2.4 V
≤ VDD ≤ 3.6 V
15
-
ns
2.0 V
≤ VDD < 2.4 V [2]
20
-
ns
tDH
data hold time
in SPI mode
0-
ns
tv(Q)
data output valid time
in SPI mode
-10
ns
th(Q)
data output hold time
in SPI mode
0-
ns
SSP slave
Tcy(PCLK)
PCLK cycle time
13.9
-
ns
tDS
data set-up time
in SPI mode
0-
ns
tDH
data hold time
in SPI mode
3
× Tcy(PCLK) + 4
-
ns
tv(Q)
data output valid time
in SPI mode
-3
× Tcy(PCLK) + 11
ns
th(Q)
data output hold time
in SPI mode
-2
× Tcy(PCLK) + 5
ns
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