參數(shù)資料
型號: LPC1751FBD80
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Cortex-M3 with 32 kB flash, 8 kB SRAM, USB 2.0 Device, CAN, 12-bit ADC
中文描述: 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT315-1, 80 PIN
文件頁數(shù): 55/74頁
文件大?。?/td> 1572K
代理商: LPC1751FBD80
LPC1759_58_56_54_52_51
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 29 March 2011
55 of 74
NXP Semiconductors
LPC1759/58/56/54/52/51
32-bit ARM Cortex-M3 microcontroller
11.8 USB interface
[1]
Characterized but not implemented as production test. Guaranteed by design.
Table 15.
C
L
= 50 pF; R
pu
= 1.5 k
on D+ to V
DD(3V3)
; 3.0 V
V
DD(3V3)
3.6 V.
Symbol
Parameter
t
r
rise time
t
f
fall time
t
FRFM
differential rise and fall time
matching
V
CRS
output signal crossover voltage
t
FEOPT
source SE0 interval of EOP
t
FDEOP
source jitter for differential transition
to SE0 transition
t
JR1
receiver jitter to next transition
t
JR2
receiver jitter for paired transitions
t
EOPR1
EOP width at receiver
Dynamic characteristics: USB pins (full-speed)
Conditions
10 % to 90 %
10 % to 90 %
t
r
/ t
f
Min
8.5
7.7
-
Typ
-
-
-
Max
13.8
13.7
109
Unit
ns
ns
%
1.3
160
2
-
-
-
2.0
175
+5
V
ns
ns
see
Figure 20
see
Figure 20
18.5
9
-
-
-
+18.5
+9
-
ns
ns
ns
10 % to 90 %
must reject as
EOP; see
Figure 20
must accept as
EOP; see
Figure 20
[1]
40
t
EOPR2
EOP width at receiver
[1]
82
-
-
ns
Fig 20. Differential data-to-EOP transition skew and EOP width
002aab561
T
PERIOD
differential
data lines
crossover point
source EOP width: t
FEOPT
receiver EOP width: t
EOPR1
, t
EOPR2
crossover point
extended
differential data to
SE0/EOP skew
n
×
T
PERIOD
+ t
FDEOP
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