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參數(shù)資料
| 型號： | LPC2103FBD48,151 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 30/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ARM7 MCU FLASH 32K 48-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs ARM7 Architecture ARM7 Memory |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | LPC2100 |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 70MHz |
| 連通性： | I²C，Microwire，SPI，SSI，SSP，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.65 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 704 (CN2011-ZH PDF) |
| 配用： | 568-4310-ND - EVAL BOARD LPC2158 W/LCD 568-4302-ND - BOARD EVAL LPC210X KS2103 JLINK 568-4301-ND - BOARD EVAL LPC210X KS2103 568-4300-ND - BOARD EVAL LPC210X MCB2103 568-4297-ND - BOARD EVAL LPC21XX MCB2100 MCB2103UME-ND - BOARD EVAL MCB2103 + ULINK-ME MCB2103U-ND - BOARD EVAL MCB2103 + ULINK2 622-1013-ND - BOARD FOR LPC2103 48-LQFP 622-1008-ND - BOARD FOR LPC9103 10-HVSON 622-1005-ND - USB IN-CIRCUIT PROG ARM7 LPC2K |
| 其它名稱： | 568-2094 935280966151 LPC2103FBD48-S |
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PIC18F85J90 FAMILY
DS39770C-page 36
2010 Microchip Technology Inc.
3.2
Control Registers
The OSCCON register (Register 3-1) controls the main
aspects of the device clock’s operation. It selects the
oscillator type to be used, which of the power-managed
modes to invoke and the output frequency of the
INTOSC source. It also provides status on the
oscillators.
The OSCTUNE register (Register 3-2) controls the
tuning and operation of the internal oscillator block. It
also implements the PLLEN bits, which control the
operation of the Phase Locked Loop (PLL) in Internal
Oscillator modes (see Section 3.4.3 “PLL Frequency
REGISTER 3-1:
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0
R/W-1
R/W-0
R(1)
R-0
R/W-0
IDLEN
IRCF2(2)
IRCF1(2)
IRCF0(2)
OSTS
IOFS
SCS1(4)
SCS0(4)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IDLEN: Idle Enable bit
1
= Device enters an Idle mode when a SLEEP instruction is executed
0
= Device enters Sleep mode when a SLEEP instruction is executed
bit 6-4
IRCF<2:0>: INTOSC Source Frequency Select bits(2)
111
= 8 MHz (INTOSC drives clock directly)
110
= 4 MHz
101
= 2 MHz
100
= 1 MHz (default)
011
= 500 kHz
010
= 250 kHz
001
= 125 kHz
000
= 31 kHz (from either INTOSC/256 or INTRC)(3)
bit 3
OSTS: Oscillator Start-up Time-out Status bit(1)
1
= Oscillator Start-up Timer (OST) time-out has expired; primary oscillator is running
0
= Oscillator Start-up Timer (OST) time-out is running; primary oscillator is not ready
bit 2
IOFS: INTOSC Frequency Stable bit
1
= Fast RC oscillator frequency is stable
0
= Fast RC oscillator frequency is not stable
bit 1-0
SCS<1:0:> System Clock Select bits(4)
11
= Internal oscillator block
10
= Primary oscillator
01
= Timer1 oscillator
When FOSC2 = 1:
00
= Primary oscillator
When FOSC2 = 0:
00
= Internal oscillator
Note 1:
Reset state depends on state of the IESO Configuration bit.
2:
Modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing
the device clocks.
3:
Source selected by the INTSRC bit (OSCTUNE<7>), see text.
4:
Modifying these bits will cause an immediate clock source switch.
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