參數(shù)資料
型號: LPC2103FBD48,151
廠商: NXP Semiconductors
文件頁數(shù): 37/37頁
文件大?。?/td> 0K
描述: IC ARM7 MCU FLASH 32K 48-LQFP
產(chǎn)品培訓(xùn)模塊: Migrating from 8/16-Bit MCUs to 32-Bit ARMs
ARM7 Architecture
ARM7 Memory
標(biāo)準包裝: 250
系列: LPC2100
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 70MHz
連通性: I²C,Microwire,SPI,SSI,SSP,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-LQFP
包裝: 托盤
產(chǎn)品目錄頁面: 704 (CN2011-ZH PDF)
配用: 568-4310-ND - EVAL BOARD LPC2158 W/LCD
568-4302-ND - BOARD EVAL LPC210X KS2103 JLINK
568-4301-ND - BOARD EVAL LPC210X KS2103
568-4300-ND - BOARD EVAL LPC210X MCB2103
568-4297-ND - BOARD EVAL LPC21XX MCB2100
MCB2103UME-ND - BOARD EVAL MCB2103 + ULINK-ME
MCB2103U-ND - BOARD EVAL MCB2103 + ULINK2
622-1013-ND - BOARD FOR LPC2103 48-LQFP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
622-1005-ND - USB IN-CIRCUIT PROG ARM7 LPC2K
其它名稱: 568-2094
935280966151
LPC2103FBD48-S
LPC2101_02_03_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 2 June 2009
9 of 37
NXP Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
[1]
5 V tolerant (if VDD(3V3) and VDDA ≥ 3.0 V) pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.
[2]
Open-drain 5 V tolerant (if VDD(3V3) and VDDA ≥ 3.0 V) digital I/O I2C-bus 400 kHz specication compatible pad. It requires external
pull-up to provide an output functionality. Open-drain conguration applies to ALL functions on that pin.
[3]
5 V tolerant (if VDD(3V3) and VDDA ≥ 3.0 V) pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and
analog input function. If congured for an input function, this pad utilizes built-in glitch lter that blocks pulses shorter than 3 ns. When
congured as an ADC input, digital section of the pad is disabled.
[4]
5 V tolerant (if VDD(3V3) and VDDA ≥ 3.0 V) pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.
If congured for an input function, this pad utilizes built-in glitch lter that blocks pulses shorter than 3 ns.
[5]
A LOW level during reset on pin P0.14 is considered as an external hardware request to start the ISP command handler.
[6]
Open-drain 5 V tolerant (if VDD(3V3) and VDDA ≥ 3.0 V) digital I/O I2C-bus 400 kHz specication compatible pad. It requires external
pull-up to provide an output functionality. Open-drain conguration applies only to I2C function on that pin.
[7]
Pad provides special analog functionality.
[8]
For lowest power consumption, pin should be left oating when the RTC is not used.
[9]
See
LPC2101/02/03 User manual UM10161 for details.
VSS
7, 19, 43
I
Ground: 0 V reference.
VSSA
31
I
Analog ground: 0 V reference. This should be nominally the same voltage as
VSS but should be isolated to minimize noise and error.
VDDA
42
I
Analog 3.3 V power supply: This should be nominally the same voltage as
VDD(3V3) but should be isolated to minimize noise and error. The level on this
pin also provides a voltage reference level for the ADC.
VDD(1V8)
5I
1.8 V core power supply: This is the power supply voltage for internal
circuitry and the on-chip PLL.
VDD(3V3)
17, 40
I
3.3 V pad power supply: This is the power supply voltage for the I/O ports.
VBAT
4
I
RTC power supply: 3.3 V on this pin supplies the power to the RTC.
Table 3.
Pin description …continued
Symbol
Pin
Type
Description
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