參數(shù)資料
型號: LPC2364FBD100
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: ARM7 with 128 kB flash, 34 kB SRAM, Ethernet, USB 2.0 Device, CAN, and 10-bit ADC
封裝: LPC2364FBD100<SOT407-1 (LQFP100)|<<http://www.nxp.com/packages/SOT407-1.html<1<Always Pb-free,;
文件頁數(shù): 25/69頁
文件大?。?/td> 517K
代理商: LPC2364FBD100
LPC2364_65_66_67_68
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 20 October 2011
25 of 69
NXP Semiconductors
LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers
Double buffer implementation for Bulk and Isochronous endpoints.
7.11 CAN controller and acceptance filters (LPC2364/66/68 only)
The Controller Area Network (CAN) is a serial communications protocol which efficiently
supports distributed real-time control with a very high level of security. Its domain of
application ranges from high-speed networks to low cost multiplex wiring.
The CAN block is intended to support multiple CAN buses simultaneously, allowing the
device to be used as a gateway, switch, or router among a number of CAN buses in
industrial or automotive applications.
Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN
Library block, but the 8-bit registers of those devices have been combined in 32-bit words
to allow simultaneous access in the ARM environment. The main operational difference is
that the recognition of received Identifiers, known in CAN terminology as Acceptance
Filtering, has been removed from the CAN controllers and centralized in a global
Acceptance Filter.
7.11.1
Features
Two CAN controllers and buses.
Data rates to 1 Mbit/s on each bus.
32-bit register and RAM access.
Compatible with
CAN specification 2.0B, ISO 11898-1
.
Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN
buses.
Acceptance Filter can provide FullCAN-style automatic reception for selected
Standard Identifiers.
FullCAN messages can generate interrupts.
7.12 10-bit ADC
The LPC2364/65/66/67/68 contain one ADC. It is a single 10-bit successive
approximation ADC with six channels.
7.12.1
Features
10-bit successive approximation ADC.
Input multiplexing among 6 pins.
Power-down mode.
Measurement range 0 V to V
i(VREF)
.
10-bit conversion time
2.44
s.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition of input pin or Timer Match signal.
Individual result registers for each ADC channel to reduce interrupt overhead.
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