參數(shù)資料
型號: LPC2387FBD100
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: Single-chip 16-bit-32-bit MCU; 512 kB flash with ISP-IAP, Ethernet, USB 2.0 device-host-OTG, CAN, and 10-bit ADC-DAC
封裝: LPC2387FBD100<SOT407-1 (LQFP100)|<<http://www.nxp.com/packages/SOT407-1.html<1<Always Pb-free,;
文件頁數(shù): 22/64頁
文件大?。?/td> 447K
代理商: LPC2387FBD100
LPC2387
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 10 February 2011
22 of 64
NXP Semiconductors
LPC2387
Single-chip 16-bit/32-bit MCU
7.11.1
Features
Two CAN controllers and buses.
Data rates to 1 Mbit/s on each bus.
32-bit register and RAM access.
Compatible with
CAN specification 2.0B, ISO 11898-1
.
Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN
buses.
Acceptance Filter can provide FullCAN-style automatic reception for selected
Standard Identifiers.
Full CAN messages can generate interrupts.
7.12 10-bit ADC
The LPC2387 contains one ADC. It is a single 10-bit successive approximation ADC with
six channels.
7.12.1
Features
10-bit successive approximation ADC.
Input multiplexing among 6 pins.
Power-down mode.
Measurement range 0 V to V
i(VREF)
.
10-bit conversion time
2.44
μ
s.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition of input pin or Timer Match signal.
Individual result registers for each ADC channel to reduce interrupt overhead.
7.13 10-bit DAC
The DAC allows the LPC2387 to generate a variable analog output. The maximum output
value of the DAC is V
i(VREF)
.
7.13.1
Features
10-bit DAC
Resistor string architecture
Buffered output
Power-down mode
Selectable output drive
7.14 UARTs
The LPC2387 contains four UARTs. In addition to standard transmit and receive data
lines, UART1 also provides a full modem control handshake interface.
The UARTs include a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
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