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參數(shù)資料
| 型號(hào)： | LPC47B34X |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 128 Pin Enhanced Super I/O with LPC Interface for Consumer Applications |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP128 |
| 封裝： | QFP-128 |
| 文件頁(yè)數(shù)： | 143/250頁(yè) |
| 文件大?。?/td> | 645K |
| 代理商： | LPC47B34X |
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WATCH DOG TIMER
The LPC47B34x contains a Watch Dog Timer (WDT). The Watch Dog Time-out status bit may be
mapped to an interrupt through the WDT_CFG Register (Runtime register at offset 54h).
The LPC47B34x's WDT has a programmable time-out ranging from 1 to 255 minutes with one minute
resolution, or 1 to 255 seconds with 1 second resolution. The units of the WDT timeout value are
selected via bit[7] of the WDT_TIMEOUT register. The WDT time-out value is set through the
WDT_VAL register. Setting the WDT_VAL register to 0x00 disables the WDT function (this is its
power on default). Setting the WDT_VAL to any other non-zero value will cause the WDT to reload
and begin counting down from the value loaded. When the WDT count value reaches zero the
counter stops and sets the Watchdog time-out status bit in the WDT_CTRL Register. Note:
Regardless of the current state of the WDT, the WDT time-out status bit can be directly set or cleared
by the Host CPU.
There are three system events which can reset the WDT. These are a Keyboard Interrupt, a Mouse
Interrupt, or I/O reads/writes to address 0x201 (an external Joystick Port). The effect on the WDT for
each of these system events may be individually enabled or disabled through bits in the WDT_CFG
register. When a system event is enabled through the WDT_CFG register, the occurrence of that
event will cause the WDT to reload the value stored in WDT_VAL and reset the WDT time-out status
bit if set. If all three system events are disabled the WDT will inevitably time out.
The Watch Dog Timer may be configured to generate an interrupt on the rising edge of the Time-out
status bit. The WDT interrupt is mapped to an interrupt channel through the WDT_CFG Register.
When mapped to an interrupt the interrupt request pin reflects the value of the WDT time-out status
bit.
The host may force a Watch Dog time-out to occur by writing a "1" to bit 2 of the WDT_CTRL (Force
WD Time-out) Register. Writing a "1" to this bit forces the WDT count value to zero and sets bit 0 of
the WDT_CTRL (Watch Dog Status). Bit 2 of the WDT_CTRL is self-clearing.
Watchdog timer output signal (WDO) is on pin 54, muxed with GP33. If this function is selected for
this pin, the pin will be an output, and the pin will go active when the internal watchdog timer signal
goes active. The polarity is selected via the polarity bit in the GPIO control register. The output buffer
type will default to push-pull, but it can be configured as open drain through bit 7 of the GPIO control
register.
See the Runtime Registers section for a description on these registers.
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