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參數(shù)資料
| 型號(hào)： | LPC47B34X |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 128 Pin Enhanced Super I/O with LPC Interface for Consumer Applications |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP128 |
| 封裝： | QFP-128 |
| 文件頁(yè)數(shù)： | 150/250頁(yè) |
| 文件大小： | 645K |
| 代理商： | LPC47B34X |
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INTRUDER DETECTION
An intrusion event can be detected as described below.
A switch connected to the chassis cover can be used to indicate if the cover is on or off. When the
cover is on, the switch is open and the nINTRSN input will be floating. When the cover is off, the
switch is closed and the nINTRSN input will be shorted to ground.
Whenever the nINTRSN input goes low, the INTRUSION bit is set. This bit remains set until cleared
by software. This bit and input logic are powered by VBAT so that an Alarm condition is detected and
stored even if VTR is removed.
Intrusion Bit
The INTRUSION bit is on the Intrusion/Oscillator Select Register. This register is powered by VTR
and battery backed up.
The INTRUSION bit will default to ‘1’ on VBAT POR (battery removed and replaced or battery voltage
below 1.2V). The INTRUSION bit will default to ‘1’ on a VTR POR if an intrusion event occurs under
battery power only or if a VBAT POR occurs.
Writing ‘0’ to the INTRUSION bit will clear it if the nINTRSN pin is low. Writing ‘1’ to the INTRUSION
bit has no effect.
See the Intrusion/Oscillator Select register description (offset 0x5E) in the “Runtime Registers”
section.
PME and SMI Generation
There are SMI status and enable bits and PME status and enable bits for the intrusion event. See the
SMI and PME runtime registers for the location and description of the corresponding INTRUSION bits
(PME_STS9, PME_EN9, SMI_STS1, SMI_EN1). The SMI and PME status bits are set under VCC
power, or VTR power. The SMI and PME status bits are cleared on a write of ‘1’ and on VTR POR.
These bits cannot be cleared until the nINTRSN pin goes low.
These bits function in one of three cases:
Case 1. An intrusion occurs under battery power only or a VBAT POR occurs. In this case, the event
will be latched under battery power and the “INTRUSION” PME and SMI status bits will be set when
VTR returns. Therefore, the PME and SMI status bits will have two possible default values on VTR
POR, depending on whether or not the intrusion event occurred under battery power. When VTR
returns, no enable bits are set, so there will be no PME or SMI generated. When VCC goes active,
and the OS sets the enable bits, a PME and/or SMI will be generated. If the corresponding PME
enable bit is set, a PME will be generated under VCC power. If the corresponding SMI enable bit is
set, an SMI will be generated under VCC power. Therefore, in this case, setting the enable bit (low-to-
high edge) will trigger the generation of the PME and SMI.
Case 2. An intrusion occurs under VTR power (VCC=0). In this case, the “INTRUSION” PME and SMI
status bits will be set. If the corresponding PME enable bit is set, a PME will be generated under VTR
power. If the corresponding SMI enable bit is set, an SMI will be generated under VCC power, since
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