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參數(shù)資料
| 型號(hào)： | LPC47B34X |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 128 Pin Enhanced Super I/O with LPC Interface for Consumer Applications |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP128 |
| 封裝： | QFP-128 |
| 文件頁(yè)數(shù)： | 144/250頁(yè) |
| 文件大小： | 645K |
| 代理商： | LPC47B34X |
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144
SYSTEM MANAGEMENT INTERRUPT (SMI)
The LPC47B34x implements a “group” nIO_SMI output pin. The System Management Interrupt is a
non-maskable interrupt with the highest priority level used for OS transparent power management.
The nIO_SMI group interrupt output consists of the enabled interrupts from Super I/O Device
Interrupts, Low Battery Warning, Intrusion, Ring and many of the GPIOs pins. The nIO_SMI pin can
be programmed to be active high or active low via the polarity bit in the GP46 register. The output
buffer type of the pin can be programmed to be open-drain or push-pull via bit 7 of the GP46 register.
The nIO_SMI pin defaults to active low, open-drain output.
The interrupts are enabled onto the group nIO_SMI output via the SMI Enable Registers 1 to 7. The
nIO_SMI output is then enabled onto the group nIO_SMI output pin via bit[7] in the SMI Enable
Register 2. The SMI output can also be enabled onto the serial IRQ stream (IRQ2) via Bit[6] in the
SMI Enable Register 2.
An example logic equation for the nIO_SMI output for SMI registers 1 and 2 is as follows:
nIO_SMI = (EN_PINT and IRQ_PINT) or (EN_U2INT and IRQ_U2INT) or (EN_U1INT and
IRQ_U1INT) or (EN_FINT and IRQ_FINT) or (EN_WDT and IRQ_WDT) or (EN_MINT and
IRQ_MINT) or (EN_KINT and IRQ_KINT) or (EN_IRINT and IRQ_IRINT)
SMI Registers
The SMI event bits for the GPIOs and the Fan tachometer events are located in the SMI status and
Enable registers 3-7. The polarity of the edge used to set the status bit and generate an SMI is
controlled by the polarity bit of the control registers. For non-inverted polarity (default) the status bit is
set on the low-to-high edge. If the EETI function is selected for a GPIO then both a high-to-low and a
low-to-high edge will set the corresponding SMI status bit. Status bits for the GPIOs are cleared on a
write of ‘1’.
Pins P12 and P16 enable SMI event on single high-to-low edge or on both high-to-low and low-to-high
edges. Default is single edge. P12 also has a polarity select bit in the configuration register 0xF0 in
Logical Device 7. The register that selects the edge, Edge Select register, is located at the address
programmed in the Base I/O Address register in the Logical Device A at an offset of 2Ch. Refer also
to PME Status and Enable register 2. See the Runtime Registers section for a description of these
registers.
Note that P12 and P16 pins are cleared on by write of ‘1’.
The SMI logic for these events is implemented such that the output of the status bit for each event is
combined with the corresponding enable bit in order to generate an SMI.
The SMI registers are accessed at an offset from Runtime Registers Block (see Runtime register
section for more information).
The SMI event bits for the super I/O devices are located in the SMI status and enable register 1 and 2.
All of these status bits are cleared at the source except for IRINT, which is cleared by a read of the
SMI_STS2 register; these status bits are not cleared by a write of ‘1’. The SMI logic for these events is
implemented such that each event is directly combined with the corresponding enable bit in order to
generate an SMI.
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