參數(shù)資料
型號: LRS1331
廠商: Sharp Corporation
英文描述: Stacked Chip 16M Flash Memory and 4M SRAM
中文描述: 堆疊1,600閃存芯片和4M的SRAM
文件頁數(shù): 1/26頁
文件大?。?/td> 216K
代理商: LRS1331
Data Sheet
1
LRS1331
Stacked Chip
Data Sheet
16M Flash Memory and 4M SRAM
FEATURES
Flash Memory and SRAM
Stacked Die Chip Scale Package
72-ball 8 mm × 11 mm CSP plastic package
Power supply: 2.7 V to 3.6 V
Operating temperature: -25°C to +85°C
Flash Memory
– Access time (MAX.): 90 ns
– Operating current (MAX.)
(The current for F-V
CC
pin and F-V
CCW
pin):
– Read: 25 mA (t
CYCLE
= 200 ns)
– Word write: 57 mA
– Block erase: 42 mA
– Standby current (the current for F-V
CC
pin): 15 μA
(MAX. F-RP
GND ± 0.2 V)
– Optimized array blocking architecture
– Two 4K-word boot blocks
– Six 4K-word parameter blocks
– Thirty-one 32K-word main blocks
– Bottom boot location
– Extended cycling capability
– 100,000 block erase cycles
– Enhanced automated suspend options
– Word write suspend to read
– Block erase suspend to word write
– Block erase suspend to read
SRAM
– Access time (MAX.): 85 ns
– Operating current: 45 mA (MAX.)
– Standby current: 15 μA (MAX.)
– Data retention current: 2 μA (MAX.)
DESCRIPTION
The LRS1331 is a combination memory organized as
1,048,576 × 16-bit flash memory and 262,144 × 16-bit
static RAM in one package.
PIN CONFIGURATION
Figure 1. LRS1331 Pin Configuration
A
INDEX
A
11
A
15
NC
NC
NC
A
14
A
9
1
2
3
4
5
6
7
A
16
DQ
15
DQ
14
S-V
CC
A
8
A
10
T
1
S-A
17
DQ
13
DQ
12
GND
T
4
F-WE
F-RY/
BY
F-RP
T
2
F-WP
F-V
PP
F-A
19
DQ
11
T
3
B
C
D
E
F
S-LB
S-UB
S-OE
NC
DQ
9
8
DQ
6
DQ
10
DQ
8
F-A
18
F-A
17
A
7
A
6
A
3
A
2
NC
NC
G
H
NC
A
5
A
4
A
0
F-OE
F-CE
F-GND
NC
NC
F-GND
A
12
A
13
9
10
S-WE
DQ
4
S-CE
2
DQ
2
DQ
0
11
A
1
NC
NC
NC
12
DQ
7
DQ
5
F-V
CC
DQ
3
DQ
1
S-CE
1
NC
LRS1331-1
TOP VIEW
72-BALL FBGA
NOTE:
All F-GND and S-GND pins are connected on the board.
Two NC pins at the corner are connected.
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