參數(shù)資料
型號(hào): LTC1407AIMSE
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: Serial 12-Bit/14-Bit, 3Msps Simultaneous Sampling Simultaneous Sampling
中文描述: 2-CH 14-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO10
封裝: PLASTIC, MSOP-10
文件頁(yè)數(shù): 15/24頁(yè)
文件大?。?/td> 443K
代理商: LTC1407AIMSE
15
LTC1407/LTC1407A
1407f
APPLICATIOU
W
U
U
POWER-DOWN MODES
Upon power-up, the LTC1407/LTC1407A are initialized to
the active state and is ready for conversion. The Nap and
Sleep mode waveforms show the power down modes for
the LTC1407/LTC1407A. The SCK and CONV inputs con-
trol the power down modes (see Timing Diagrams). Two
rising edges at CONV, without any intervening rising
edges at SCK, put the LTC1407/LTC1407A in Nap mode
and the power drain drops from 14mW to 6mW. The
internal reference remains powered in Nap mode. One or
more rising edges at SCK wake up the LTC1407/LTC1407A
for service very quickly and CONV can start an accurate
conversion within a clock cycle. Four rising edges at
CONV, without any intervening rising edges at SCK, put
the LTC1407/LTC1407A in Sleep mode and the power
drain drops from 14mW to 10
μ
W. One or more rising
edges at SCK wake up the LTC1407/LTC1407A for opera-
tion. The internal reference (V
REF
) takes 2ms to slew and
settle with a 10
μ
F load. Using sleep mode more frequently
compromises the settled accuracy of the internal refer-
ence. Note that for slower conversion rates, the Nap and
Sleep modes can be used for substantial reductions in
power consumption.
Figure 5. Recommended Layout
1407 F05
相關(guān)PDF資料
PDF描述
LTC1407IMSE Serial 12-Bit/14-Bit, 3Msps Simultaneous Sampling Simultaneous Sampling
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LTC1409CG 12-Bit, 800ksps Sampling A/D Converter with Shutdown
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