參數(shù)資料
型號(hào): LTC1407AIMSE
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: Serial 12-Bit/14-Bit, 3Msps Simultaneous Sampling Simultaneous Sampling
中文描述: 2-CH 14-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO10
封裝: PLASTIC, MSOP-10
文件頁數(shù): 4/24頁
文件大小: 443K
代理商: LTC1407AIMSE
4
LTC1407/LTC1407A
1407f
SYMBOL
f
SAMPLE(MAX)
PARAMETER
Maximum Sampling Frequency per Channel
(Conversion Rate)
Minimum Sampling Period (Conversion + Acquisiton Period)
Clock Period
Conversion Time
Minimum Positive or Negative SCLK Pulse Width
CONV to SCK
Setup Time
SCK
Before CONV
Minimum Positive or Negative CONV Pulse Width
SCK
to Sample Mode
CONV to Hold Mode
32nd SCK
to CONV
Interval (Affects Acquisition Period)
Minimum Delay from SCK
to Valid Bits 0 Through 11
SCK to Hi-Z at SDO
Previous SDO Bit Remains Valid After SCK
V
REF
Settling Time After Sleep-to-Wake Transition
CONDITIONS
MIN
1.5
TYP
MAX
UNITS
MHz
G
t
THROUGHPUT
t
SCK
t
CONV
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
12
G
667
10000
ns
ns
(Note 16)
(Note 6)
(Note 6)
(Notes 6, 10)
(Note 6)
(Note 6)
(Note 6)
(Notes 6, 11)
(Notes 6, 7, 13)
(Notes 6, 12)
(Notes 6, 12)
(Notes 6, 12)
(Notes 6, 14)
G
19.6
32
2
3
0
4
4
1.2
45
8
6
2
34
SCLK cycles
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
2
The
G
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25
°
C. With internal reference, V
DD
= 3V.
SYMBOL
V
DD
I
DD
PARAMETER
Supply Voltage
Supply Current
CONDITIONS
MIN
2.7
TYP
MAX
3.6
7.0
1.5
15
10
UNITS
V
Active Mode, f
SAMPLE
= 1.5Msps
Nap Mode
Sleep Mode (LTC1407)
Sleep Mode (LTC1407A)
Active Mode with SCK in Fixed State (Hi or Lo)
G
G
4.7
1.1
2.0
2.0
12
mA
mA
μ
A
μ
A
mW
PD
TIW
Power Dissipation
POWER REQUIRE E TS
The
G
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25
°
C. V
DD
= 3V.
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
All voltage values are with respect to ground GND.
Note 3:
When these pins are taken below GND or above V
DD
, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than V
DD
without latchup.
Note 4:
Offset and range specifications apply for a single-ended CH0
+
or
CH1
+
input with CH0
or CH1
grounded and using the internal 2.5V
reference.
Note 5:
Integral linearity is tested with an external 2.55V reference and is
defined as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band.
Note 6:
Guaranteed by design, not subject to test.
Note 7:
Recommended operating conditions.
Note 8:
The analog input range is defined for the voltage difference
between CH0
+
and CH0
or CH1
+
and CH1
.
Note 9:
The absolute voltage at CH0
+
,
CH0
, CH1
+
and CH1
must be
within this range.
Note 10:
If less than 3ns is allowed, the output data will appear one clock
cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11:
Not the same as aperture delay. Aperture delay (1ns) is the
difference between the 2.2ns delay through the sample-and-hold and the
1.2ns CONV to Hold mode delay.
Note 12:
The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13:
The time period for acquiring the input signal is started by the
32nd rising clock and it is ended by the rising edge of CONV.
Note 14:
The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10
μ
F capacitive load.
Note 15:
The full power bandwidth is the frequency where the output code
swing drops by 3dB with a 2.5V
P-P
input sine wave.
Note 16:
Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock period.
Note 17:
The LTC1407A is measured and specified with 14-bit Resolution
(1LSB = 152
μ
V) and the LTC1407 is measured and specified with 12-bit
Resolution (1LSB = 610
μ
V).
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