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參數(shù)資料
| 型號(hào)： | LTC2153IUJ-14#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 24/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT DUAL 310MSPS 40QFN |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 310M |
| 數(shù)據(jù)接口： | 并聯(lián)，串行，SPI |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 479mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 40-QFN（6x6） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)差分 |
| 配用： | DC1371A-ND - BOARD USB DATA ACQUISITION HS |
9
215314f
LTC2153-14
pin FuncTions
SCK (Pin 38): Serial Interface Clock Input. In serial
programming mode, (PAR/SER = 0V), SCK is the serial
interfaceclockinput.Inparallelprogrammingmode(PAR/
SER = VDD), SCK controls the sleep mode (see Table 2).
CS (Pin 39): Serial Interface Chip Select Input. In serial
programming mode, (PAR/SER = 0V), CS is the serial in-
terface chip select input. When CS is low, SCK is enabled
for shifting data on SDI into the mode control registers. In
parallelprogrammingmode(PAR/SER=VDD),CScontrols
the clock duty cycle stabilizer (see Table 2).
PAR/SER (Pin 40): Programming Mode Selection Pin.
Connect to ground to enable the serial programming
mode. CS, SCK, SDI and SDO become a serial interface
that control the A/D operating modes. Connect to VDD to
enabletheparallelprogrammingmodewhereCS,SCKand
SDI become parallel logic inputs that control a reduced
set of the A/D operating modes. PAR/SER should be con-
nected directly to ground or the VDD of the part and not
be driven by a logic signal.
LVDS Outputs (DDR LVDS)
The following pins are differential LVDS outputs. The
output current level is programmable. There is an optional
internal 100 termination resistor between the pins of
each LVDS output pair.
D0_1–/D0_1+ to D12_13–/D12_13+ (Pins 16/17, 18/19,
22/23, 24/25, 28/29, 31/32, 33/34): Double-Data Rate
Digital Outputs. Two data bits are multiplexed onto each
differential output pair. The even data bits (D0, D2, D4,
D6, D8, D10, D12) appear when CLKOUT+ is low. The odd
data bits (D1, D3, D5, D7, D9, D11, D13) appear when
CLKOUT+ is high.
CLKOUT–, CLKOUT+ (Pins 26, 27): Data Output Clock.
The digital outputs normally transition at the same time
as the falling and rising edges of CLKOUT+. The phase of
CLKOUT+ can also be delayed relative to the digital outputs
by programming the mode control registers.
OF–, OF+ (Pins 14, 15): Over/Underflow Digital Output.
OF+ is high when an overflow or underflow has occurred.
This underflow is valid only when CLKOUT+ is low. In the
second half clock cycle, the overflow is set to 0.
FuncTional block DiagraM
Figure 1. Functional Block Diagram
S/H
VCM
BUFFER
GND
VCM
0.1F
CORRECTION
LOGIC
OUTPUT
DRIVERS
14-BIT
PIPELINED
ADC
CLOCK/DUTY
CYCLE CONTROL
1.25V
REFERENCE
RANGE
SELECT
CLOCK
ANALOG
INPUT
215314 F01
DDR
LVDS
VDD
OVDD
OGND
CS
SPI
VREF
2.2F
GND
SENSE
SCK
SDI
SDO
PAR/SER
D12_13
D0_1
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