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參數(shù)資料
| 型號： | LTC2153IUJ-14#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT DUAL 310MSPS 40QFN |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 310M |
| 數(shù)據(jù)接口： | 并聯(lián)，串行，SPI |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 479mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 40-QFN（6x6） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分 |
| 配用： | DC1371A-ND - BOARD USB DATA ACQUISITION HS |
LTC2153-14
16
215314f
Alternate Bit Polarity
Another feature that may reduce digital feedback on the
circuit board is the alternate bit polarity mode. When this
mode is enabled, all of the odd bits (D1, D3, D5, D7, D9,
D11, D13) are inverted before the output buffers. The even
bits (D0, D2, D4, D6, D8, D10, D12), OF and CLKOUT are
not affected. This can reduce digital currents in the circuit
board ground plane and reduce digital noise, particularly
for very small analog input signals.
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11, D13.) The alternate
bit polarity mode is independent of the digital output ran-
domizer—either both or neither function can be on at the
same time. The alternate bit polarity mode is enabled by
serially programming mode control register A4.
Digital Output Test Patterns
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes that force the A/D data
outputs (OF, D13 to D0) to known values:
All 1s: All outputs are 1
All 0s: All outputs are 0
Alternating: Outputs change from all 1s to all 0s on
alternating samples
Checkerboard:Outputschangefrom101010101010101
to 010101010101010 on alternating samples.
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the test patterns override all other formatting modes:
2’s complement, randomizer, alternate-bit polarity.
Output Disable
The digital outputs may be disabled by serially program-
ming mode control register A3. All digital outputs includ-
ing OF and CLKOUT are disabled. The high impedance
disabled state is intended for long periods of inactivity,
it is not designed for multiplexing the data bus between
multiple converters.
Sleep Mode
The A/D may be placed in sleep mode to conserve power.
In sleep mode the entire A/D converter is powered down,
resulting in < 5mW power consumption. If the encode
input signal is not disabled the power consumption will
be higher (up to 5mW at 310MHz). Sleep mode is enabled
by mode control register A1 (serial programming mode),
or by SCK (parallel programming mode).
The amount of time required to recover from sleep mode
depends on the size of the bypass capacitor on VREF . For
the suggested value in Figure 1, the A/D will stabilize after
0.1ms + 2500 tp where tp is the period of the sampling
clock.
Nap Mode
In nap mode the A/D core is powered down while the
internal reference circuits stay active, allowing faster
wake-up. Recovering from nap mode requires at least 100
clock cycles. Nap mode is enabled by setting register A1
in the serial programming mode.
Wake-up time from nap mode is guaranteed only if the
clock is kept running, otherwise sleep mode wake-up
conditions apply.
DEVICE PROGRAMMING MODES
The operating modes of the LTC2153-14 can be pro-
grammed by either a parallel interface or a simple serial
interface. The serial interface has more flexibility and
can program all available modes. The parallel interface
is more limited and can only program some of the more
commonly used modes.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to VDD. The CS, SCK and SDI pins are binary logic
inputs that set certain operating modes. These pins can
be tied to VDD or ground, or driven by 1.8V, 2.5V, or 3.3V
CMOS logic. Table 2 shows the modes set by CS, SCK
and SDI.
applicaTions inForMaTion
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| LTC2155CUP-12#PBF | 功能描述:IC ADC DUAL 12BIT 170M 64-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
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