參數(shù)資料
型號(hào)： LTC2410CGN
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 20-Bit Universal Bus Driver With 3-State Outputs 56-SSOP -40 to 85
中文描述： 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16
封裝： 0.150 INCH, PLASTIC, SSOP-16
文件頁(yè)數(shù)： 19/44頁(yè)
文件大小： 778K
代理商： LTC2410CGN
LTC2410
19
APPLICATIU
W
U
U
CS is discharging; therefore, the internal serial clock
timing mode is automatically selected if SCK is floating. It
is important to ensure there are no external drivers pulling
SCK LOW while CS is discharging.
PRESERVING THE CONVERTER ACCURACY
The LTC2410 is designed to reduce as much as possible
the conversion result sensitivity to device decoupling,
PCB layout, antialiasing circuits, line frequency perturba-
tions and so on. Nevertheless, in order to preserve the
extreme accuracy capability of this part, some simple
precautions are desirable.
Digital Signal Levels
The LTC2410’s digital interface is easy to use. Its digital
inputs (F
O
, CS and SCK in External SCK mode of operation)
accept standard TTL/CMOS logic levels and the internal
hysteresis receivers can tolerate edge rates as slow as
100
μ
s. However, some considerations are required to take
advantage of the exceptional accuracy and low supply
current of this converter.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
While a digital input signal is in the range 0.5V to
(V
CC
–0.5V), the CMOS input receiver draws additional
current from the power supply. It should be noted that,
when any one of the digital input signals (F
O
, CS and SCK
in External SCK mode of operation) is within this range, the
LTC2410 power supply current may increase even if the
signal in question is at a valid logic level. For micropower
operation, it is recommended to drive all digital input
signals to full CMOS levels [V
IL
< 0.4V and V
OH
>
(V
CC
– 0.4V)].
During the conversion period, the undershoot and/or
overshoot of a fast digital signal connected to the LTC2410
pins may severely disturb the analog to digital conversion
process. Undershoot and overshoot can occur because of
the impedance mismatch at the converter pin when the
transition time of an external control signal is less than
twice the propagation delay from the driver to LTC2410.
For reference, on a regular FR-4 board, signal propagation
Figure 12. CS Capacitance vs t
SAMPLE
Figure 13. CS Capacitance vs Output Rate
Figure 14. CS Capacitance vs Supply Current
CAPACITANCE ON CS (pF)
1
5
6
7
1000
10000
2400 F12
4
3
10
100
100000
2
1
0
t
S
V
CC
= 5V
V
CC
= 3V
CAPACITANCE ON CS (pF)
0
S
3
4
5
1000
100000
2400 F13
2
1
0
10
100
10000
6
7
8
V
CC
= 5V
V
CC
= 3V
CAPACITANCE ON CS (pF)
1
0
S
μ
A
R
)
50
100
150
200
250
300
10
100
1000
10000
2400 F14
100000
V
CC
= 5V
V
CC
= 3V
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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