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參數資料
| 型號： | LTC2439-1 |
| 廠商： | Linear Technology Corporation |
| 元件分類： | ADC |
| 英文描述： | 8-/16-Channel 16-Bit No Latency Delta-Sigma ADC |
| 中文描述： | 8-/16-Channel 16位無延遲增量累加模數轉換器 |
| 文件頁數： | 22/28頁 |
| 文件大?。?/td> | 288K |
| 代理商： | LTC2439-1 |
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LTC2439-1
22
24391f
The effect of this input dynamic current can be analyzed
using the test circuit of Figure 13. The C
PAR
capacitor
includes the LTC2439-1 pin capacitance (5pF typical) plus
the capacitance of the test fixture used to obtain the results
shown in Figures 14 and 15. A careful implementation can
bring the total input capacitance (C
IN
+ C
PAR
) closer to 5pF
thus achieving better performance than the one predicted
by Figures 14 and 15. For simplicity, two distinct situa-
tions can be considered.
For relatively small values of input capacitance (C
IN
<
0.01
μ
F), the voltage on the sampling capacitor settles
almost completely and relatively large values for the
source impedance result in only small errors. Such values
for C
IN
will deteriorate the converter offset and gain
performance without significant benefits of signal filtering
and the user is advised to avoid them. Nevertheless, when
small values of C
IN
are unavoidably present as parasitics
of input multiplexers, wires, connectors or sensors, the
LTC2439-1 can maintain its accuracy while operating with
relative large values of source resistance as shown in
Figures 14 and 15. These measured results may be slightly
different from the first order approximation suggested
earlier because they include the effect of the actual second
order input network together with the nonlinear settling
process of the input amplifiers. For small C
IN
values, the
settling on IN
+
and IN
–
occurs almost independently and
there is little benefit in trying to match the source imped-
ance for the two pins.
Larger values of input capacitors (C
IN
> 0.01
μ
F) may be
required in certain configurations for antialiasing or gen-
eral input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When F
O
= LOW (internal oscillator and 50Hz/60Hz notch),
the typical differential input resistance is 2M
which will
generate a gain error of approximately 1LSB at full scale
for each 60
of source resistance driving IN
+
or IN
–
.
When F
O
is driven by an external oscillator with a fre-
quency f
EOSC
(external conversion clock operation), the
typical differential input resistance is 0.28 10
12
/f
EOSC
R
SOURCE
(
)
1
10
100
1k
10k
100k
+
24361 F14
3
0
1
2
V
CC
= 5V
REF
+
= 5V
REF
–
= GND
IN
+
= 5V
IN
–
= 2.5V
F
O
= GND
T
A
= 25
°
C
C
IN
= 0.01
μ
F
C
IN
= 0.001
μ
F
C
IN
= 100pF
C
IN
= 0pF
C
IN
24361 F13
V
INCM
+ 0.5V
IN
R
SOURCE
IN
+
LTC2439-1
C
PAR
20pF
C
IN
V
INCM
– 0.5V
IN
R
SOURCE
IN
–
C
PAR
20pF
Figure 13. An RC Network at IN
+
and IN
–
R
SOURCE
(
)
1
10
100
1k
10k
100k
–
24361 F15
0
–3
–2
–1
V
= 5V
REF
+
= 5V
REF
–
= GND
IN
+
= GND
IN
–
= 2.5V
F
O
= GND
T
A
= 25
°
C
C
IN
= 0.01
μ
F
C
IN
= 0.001
μ
F
C
IN
= 100pF
C
IN
= 0pF
Figure 14. +FS Error vs R
SOURCE
at IN
+
or IN
–
(Small C
IN
)
Figure 15. –FS Error vs R
SOURCE
at IN
+
or IN
–
(Small C
IN
)
APPLICATIOU
W
U
U
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