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參數(shù)資料
| 型號(hào)： | LTC2440CGN |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 24-Bit High Speed Differential delta-sigma ADC with Selectable Speed/Resolution |
| 中文描述： | 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 12/28頁 |
| 文件大小： | 316K |
| 代理商： | LTC2440CGN |
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LTC2440
12
sn2440, 2440fas
signal may be used as an interrupt for an external
microcontroller. Bit 31 (EOC) can be captured on the first
rising edge of SCK. Bit 30 is shifted out of the device on the
first falling edge of SCK. The final data bit (Bit 0) is shifted
out on the falling edge of the 31st SCK and may be latched
on the rising edge of the 32nd SCK pulse. On the falling
edge of the 32nd SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the IN
+
and IN
–
pins is maintained
within the –0.3V to (V
CC
+ 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage V
IN
from –FS = –0.5 V
REF
to
+FS = 0.5 V
REF
. For differential input voltages greater than
+FS, the conversion result is clamped to the value corre-
sponding to the +FS + 1LSB. For differential input voltages
below –FS, the conversion result is clamped to the value
corresponding to –FS – 1LSB.
SERIAL INTERFACE PINS
The LTC2440 transmits the conversion results and re-
ceives the start of conversion command through a
synchronous 2-wire, 3-wire or 4-wire interface. During
the conversion and sleep states, this interface can be
used to assess the converter status and during the data
output state it is used to read the conversion result and
program the speed/resolution.
Serial Clock Input/Output (SCK)
The serial clock signal present on SCK (Pin 13) is used to
synchronize the data transfer. Each bit of data is shifted out
the SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2440 creates its own serial clock. In the
External SCK mode of operation, the SCK pin is used as
input. The internal or external SCK mode is selected by tying
EXT (Pin 10) LOW for external SCK and HIGH for internal
SCK.
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 12), provides the
result of the last conversion as a serial bit stream (MSB
first) during the data output state. In addition, the SDO pin
is used as an end of conversion indicator during the
conversion and sleep states.
When CS (Pin 11) is HIGH, the SDO driver is switched to
a high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH on
the SDO pin. Once the conversion is complete, EOC goes
LOW. The device remains in the sleep state until the first
rising edge of SCK occurs while CS = LOW.
Table 2. LTC2440 Output Data Format
Differential Input Voltage
V
IN
*
V
IN
*
≥
0.5 V
REF
**
0.5 V
REF
** – 1LSB
0.25 V
REF
**
0.25 V
REF
** – 1LSB
0
–1LSB
Bit 31
EOC
0
0
Bit 30
DMY
0
0
Bit 29
SIG
1
1
Bit 28
MSB
1
0
Bit 27
Bit 26
Bit 25
…
Bit 0
0
1
0
1
0
1
…
…
0
1
0
0
0
0
1
1
0
0
1
0
0
1
0
1
…
…
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
1
…
…
0
1
–0.25 V
REF
**
–0.25 V
REF
** – 1LSB
–0.5 V
REF
**
V
IN
* < –0.5 V
REF
**
*The differential input voltage V
IN
= IN
+
– IN
–
. **The differential reference voltage V
REF
= REF
+
– REF
–
.
0
0
0
0
0
0
1
1
1
0
0
1
0
1
…
…
0
1
0
0
0
0
0
0
1
0
0
1
0
1
0
1
…
…
0
1
APPLICATIU
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U
U
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