- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377770 > LTC2440CGN (LINEAR TECHNOLOGY CORP) 24-Bit High Speed Differential delta-sigma ADC with Selectable Speed/Resolution PDF資料下載
參數(shù)資料
| 型號(hào)： | LTC2440CGN |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 24-Bit High Speed Differential delta-sigma ADC with Selectable Speed/Resolution |
| 中文描述： | 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 17/28頁 |
| 文件大?。?/td> | 316K |
| 代理商： | LTC2440CGN |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當(dāng)前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
LTC2440
17
sn2440, 2440fas
APPLICATIU
W
U
U
indicating the conversion result is ready. EOC = 1
(BUSY = 1) while the conversion is in progress and
EOC = 0 (BUSY = 0) once the conversion enters the low
power sleep state. On the falling edge of EOC/BUSY, the
conversion result is loaded into an internal static shift
register. The device remains in the sleep state until the
first rising edge of SCK. Data is shifted out the SDO pin
on each falling edge of SCK enabling external circuitry to
latch data on the rising edge of SCK. EOC can be latched
on the first rising edge of SCK. On the 32nd falling edge
of SCK, SDO and BUSY go HIGH (EOC = 1) indicating a
new conversion has begun.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 8.
In order to select the internal serial clock timing mode, the
EXT pin must be tied HIGH.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state. Alternatively,
BUSY (Pin 15) may be used to monitor the status of the
conversion in progress. BUSY is HIGH during the conver-
sion and goes LOW at the conclusion. It remains LOW until
the result is read from the device.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CS remains LOW. In order to prevent the device
from exiting the low power sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time t
EOCtest
after the falling edge of CS
(if EOC = 0) or t
EOCtest
after EOC goes LOW (if CS is LOW
during the falling edge of EOC). The value of t
EOCtest
is
500ns. If CS is pulled HIGH before time t
EOCtest
, the device
remains in the sleep state. The conversion result is held in
the internal static shift register.
If CS remains LOW longer than t
EOCtest
, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
Figure 8. Internal Serial Clock, Single Cycle Operation
SDO
BUSY
SCK
(INTERNAL)
CS
MSB
SIG
BIT 0
LSB
24
BIT 5
TEST EOC
BIT 27
BIT 26
BIT 28
BIT 29
BIT 30
EOC
BIT 31
SLEEP
DATA OUTPUT
CONVERSION
CONVERSION
2440 F08
<t
EOCtest
Hi-Z
Hi-Z
Hi-Z
Hi-Z
TEST EOC
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
V
CC
F
O
REF
REF
–
IN
+
IN
–
SCK
BUSY
SDO
GND
CS
EXT
2
14
3
4
13
5
6
12
1, 8, 9, 16
11
10
V
CC
15
SDI
7
REFERENCE VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
–0.5V
REF
TO 0.5V
REF
1
μ
F
4.5V TO 5.5V
LTC2440
3-WIRE
SPI INTERFACE
V
CC
200nV NOISE, 50/60Hz REJECTION
10-SPEED/RESOLUTION PROGRAMMABLE
2
μ
V NOISE, 880Hz OUTPUT RATE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC2440IGN | 24-Bit High Speed Differential delta-sigma ADC with Selectable Speed/Resolution |
| LTC2444 | 24-Bit High Speed 8-/16-Channel ADCs with Selectable Speed/Resolution |
| LTC2444C | 24-Bit High Speed 8-/16-Channel ADCs with Selectable Speed/Resolution |
| LTC2444CUHF | 24-Bit High Speed 8-/16-Channel ADCs with Selectable Speed/Resolution |
| LTC2444I | 24-Bit High Speed 8-/16-Channel ADCs with Selectable Speed/Resolution |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2440CGN#PBF | 功能描述:IC ADC DIFFER 24-BIT HS 16-SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個(gè)單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| LTC2440CGN#PBF | 制造商:Linear Technology 功能描述:24BIT ADC DELTA SIG HS 16SSOP 制造商:Linear Technology 功能描述:24BIT ADC, DELTA SIG, HS, 16SSOP |
| LTC2440CGN#TR | 功能描述:IC CONV A/D 24-BIT DIFF 16-SSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個(gè)單端，單極 |
| LTC2440CGN#TRPBF | 功能描述:IC ADC DIFFER 24-BIT HS 16-SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個(gè)單端，單極 |
| LTC2440CGNPBF | 制造商:Linear Technology 功能描述:ADC,LTC2440C 24bit diff D-S SPI SSOP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。