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參數(shù)資料
| 型號： | LTC2440CGN |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 24-Bit High Speed Differential delta-sigma ADC with Selectable Speed/Resolution |
| 中文描述： | 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 21/28頁 |
| 文件大?。?/td> | 316K |
| 代理商： | LTC2440CGN |
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LTC2440
21
sn2440, 2440fas
APPLICATIU
W
U
U
The sample rate f
S
and NULL f
N
, my also be adjusted by
driving the F
O
pin with an external oscillator. The sample
rate is f
S
= f
EOSC
/5, where f
EOSC
is the frequency of the
clock applied to F
O
. Combining a large OSR with a reduced
sample rate leads to notch frequencies f
N
near DC while
maintaining simple antialiasing requirements. A 100kHz
clock applied to F
O
results in a NULL at 0.6Hz plus all
harmonics up to 20kHz, see Figure 14. This is useful in
applications requiring digitalization of the DC component
of a noisy input signal and eliminates the need of placing
a 0.6Hz filter in front of the ADC.
An external oscillator operating from 100kHz to 20MHz
can be implemented using the LTC1799 (resistor set
SOT-23 oscillator), see Figure 22. By floating pin 4 (DIV)
of the LTC1799, the output oscillator frequency is:
f
MHz
k
R
OSC
SET
=
10
10
10
The normal mode rejection characteristic shown in Fig-
ure 14 is achieved by applying the output of the LTC1799
(with R
SET
= 100k) to the F
O
pin on the LTC2440 with SDI
tied HIGH (OSR = 32768).
Reduced Power Operation
In addition to adjusting the speed/resolution of the
LTC2440, the speed/resolution/power dissipation may
also be adjusted using the automatic sleep mode. During
the conversion cycle, the LTC2440 draws 8mA supply
current independent of the programmed speed. Once the
conversion cycle is completed, the device automatically
enters a low power sleep state drawing 8
μ
A. The device
remains in this state as long as CS is HIGH and data is not
shifted out. By adjusting the duration of the sleep state
(hold CS HIGH longer) and the duration of the conversion
cycle (programming OSR) the DC power dissipation can
be reduced, see Figure 16.
For example, if the OSR is programmed at the fastest rate
(OSR = 64, t
CONV
= 0.285ms) and the sleep state is 10ms,
the effective output rate is approximately 100Hz while the
average supply current is reduced to 240
μ
A. By further
extending the sleep state to 100ms, the effective output
rate of 10Hz draws on average 30
μ
A. Noise, power, and
speed can be optimized by adjusting the OSR (Noise/
Speed) and sleep mode duration (Power).
Figure 14. LTC2440 Normal Mode Rejection
(External Oscillator at 90kHz)
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
–40
–20
0
8
2440 F14
–60
–80
2
4
6
10
–100
–120
–140
N
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2440CGN#PBF | 功能描述:IC ADC DIFFER 24-BIT HS 16-SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| LTC2440CGN#PBF | 制造商:Linear Technology 功能描述:24BIT ADC DELTA SIG HS 16SSOP 制造商:Linear Technology 功能描述:24BIT ADC, DELTA SIG, HS, 16SSOP |
| LTC2440CGN#TR | 功能描述:IC CONV A/D 24-BIT DIFF 16-SSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
| LTC2440CGN#TRPBF | 功能描述:IC ADC DIFFER 24-BIT HS 16-SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
| LTC2440CGNPBF | 制造商:Linear Technology 功能描述:ADC,LTC2440C 24bit diff D-S SPI SSOP |
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