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參數(shù)資料
| 型號： | LTC2484IDD#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 11/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT 10-DFN |
| 標準包裝： | 2,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 6.8 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 480µW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 10-DFN（3x3） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 配用： | DC939A-ND - BOARD DELTA SIGMA ADC LTC2484 |
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LTC2484
19
2484fd
APPLICATIONS INFORMATION
VIN = IN+ – IN–, from –FS to +FS where FS = 0.5 VREF.
Outside this range, the converter indicates the overrange
or the underrange condition using distinct output codes.
Since the differential input current cancellation does not
rely on an on-chip buffer, current cancellation as well as
DC performance is maintained rail-to-rail.
Input signals applied to IN+ and IN– pins may extend by
300mV below ground and above VCC. In order to limit any
fault current, resistors of up to 5k may be added in series
with the IN+ and IN– pins without affecting the performance
of the devices. The effect of the series resistance on the
converter accuracy can be evaluated from the curves
presented in the Input Current/Reference Current sections.
In addition, series resistors will introduce a temperature
dependent offset error due to the input leakage current.
A 1nA input leakage current will develop a 1ppm offset
error on a 5k resistor if VREF = 5V. This error has a very
strong temperature dependency.
SERIAL INTERFACE TIMING MODES
The LTC2484’s 4-wire interface is SPI and MICROWIRE
compatible. This interface offers several exible modes
of operation. These include internal/external serial clock,
3- or 4-wire I/O, single cycle or continuous conversion. The
following sections describe each of these serial interface
timing modes in detail. In all these cases, the converter
can use the internal oscillator (fO = LOW or fO = HIGH)
or an external oscillator connected to the fO pin. Refer to
Table 5 for a summary.
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift
out the conversion result and a CS signal to monitor and
control the state of the conversion cycle (see Figure 5).
The serial clock mode is selected on the falling edge of CS.
To select the external serial clock mode, the serial clock
pin (SCK) must be LOW during each CS falling edge.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0
if the device is in the sleep state. Independent of CS, the
device automatically enters the low power sleep state once
the conversion is complete.
When the device is in the sleep state, its conversion result
is held in an internal static shift register. The device remains
in the sleep state until the rst rising edge of SCK is seen
while CS is LOW. The input data is then shifted in via the
SDI pin on the rising edge of SCK (including the rst rising
edge) and the output data is shifted out of the SDO pin on
each falling edge of SCK. This enables external circuitry
to latch the output on the rising edge of SCK. EOC can be
latched on the rst rising edge of SCK and the last bit of
the conversion result can be latched on the 32nd rising
edge of SCK. On the 32nd falling edge of SCK, the device
begins a new conversion. SDO goes HIGH (EOC = 1)
indicating a conversion is in progress.
Table 5. LTC2484 Interface Timing Modes
CONFIGURATION
SCK
SOURCE
CONVERSION
CYCLE CONTROL
DATA OUTPUT
CONTROL
CONNECTION
and WAVEFORMS
External SCK, Single Cycle Conversion
External
CS and SCK
Figures 5, 6
External SCK, 3-Wire I/O
External
SCK
Figure 7
Internal SCK, Single Cycle Conversion
Internal
CS
↓
CS
↓
Figures 8, 9
Internal SCK, 3-Wire I/O, Continuous Conversion
Internal
Continuous
Internal
Figure 10
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