參數(shù)資料
型號(hào)： LTC2484IDD#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 7/42頁(yè)
文件大?。?/td> 0K
描述： IC ADC 24BIT 10-DFN
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 24
采樣率（每秒）： 6.8
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 480µW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 10-WFDFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 10-DFN（3x3）
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 1 個(gè)差分，雙極
配用： DC939A-ND - BOARD DELTA SIGMA ADC LTC2484
LTC2484
15
2484fd
APPLICATIONS INFORMATION
Several applications leveraging this feature are presented
in more detail in the applications section. While operating
in this mode, the speed is set to normal independent of
control bit SPD.
Rejection Mode (FA, FB)
The LTC2484 includes a high accuracy on-chip oscilla-
tor with no required external components. Coupled with
a 4th order digital lowpass lter, the LTC2484 rejects
line frequency noise. In the default mode, the LTC2484
simultaneously rejects 50Hz and 60Hz by at least 87dB.
The LTC2484 can also be congured to selectively reject
50Hz or 60Hz to better than 110dB.
Speed Mode (SPD)
The LTC2484 continuously performs offset calibrations.
Every conversion cycle, two conversions are automatically
performed (default) and the results combined. This result is
free from offset and drift. In applications where the offset
is not critical, the autocalibration feature can be disabled
with the benet of twice the output rate.
Linearity, full-scale accuracy, full-scale drift are identical
for both 2x and 1x speed modes. In both the 1x and 2x
speed there is no latency. This enables input steps or
multiplexer channel changes to settle in a single conver-
sion cycle easing system overhead and increasing the
effective conversion rate.
Output Data Format
The LTC2484 serial output data stream is 32 bits long. The
rst 3 bits represent status information indicating the sign
and conversion state. The next 24 bits are the conversion
result, MSB rst. The remaining 5 bits are sub LSBs below
the 24-bit level. The third and fourth bit together are also
used to indicate an underrange condition (the differential
input voltage is below –FS) or an overrange condition (the
differential input voltage is above +FS).
CS may be pulled HIGH prior to outputting all 32 bits,
aborting the data out transfer and initiating a new
conversion.
Bit 31 (rst output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW when
the conversion is complete.
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign
indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0,
this bit is LOW.
Bit 28 (fourth output bit) is the most signicant bit (MSB) of
the result. This bit in conjunction with bit 29 also provides
the underrange or overrange indication. If both bit 29 and
bit 28 are HIGH, the differential input voltage is above +FS.
If both bit 29 and bit 28 are LOW, the differential input
voltage is below –FS.
The function of these bits is summarized in Table 2.
Table 2. LTC2484 Status Bits
INPUT RANGE
BIT 31
EOC
BIT 30
DMY
BIT 29
SIG
BIT 28
MSB
VIN ≥ 0.5 VREF
0011
0V ≤ VIN < 0.5 VREF
00
1/0
0
–0.5 VREF ≤ VIN < 0V
0001
VIN < –0.5 VREF
0000
Bits 28-5 are the 24-bit conversion result MSB rst.
Bits 4–0 are sub LSBs below the 24-bit level. Bits 4–0
may be included in averaging or discarded without loss
of resolution.
Data is shifted out of the SDO pin under control of the
serial clock (SCK) (see Figure 2). Whenever CS is HIGH,
SDO remains high impedance and any externally gener-
ated SCK clock pulses are ignored by the internal data
out shift register.
In order to shift the conversion result out of the device,
CS must rst be driven LOW. EOC is seen at the SDO pin
of the device once CS is pulled LOW. EOC changes in real
time from HIGH to LOW at the completion of a conversion.
This signal may be used as an interrupt for an external
microcontroller. Bit 31 (EOC) can be captured on the rst
rising edge of SCK. Bit 30 is shifted out of the device on
the rst falling edge of SCK. The nal data bit (bit 0) is
shifted out on the falling edge of the 31st SCK and may
be latched on the rising edge of the 32nd SCK pulse. On
the falling edge of the 32nd SCK pulse, SDO goes HIGH
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