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參數(shù)資料
| 型號： | LTC2484IDD#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT 10-DFN |
| 標準包裝： | 2,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 6.8 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 480µW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤 |
| 供應商設備封裝： | 10-DFN（3x3） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 配用： | DC939A-ND - BOARD DELTA SIGMA ADC LTC2484 |
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LTC2484
13
2484fd
APPLICATIONS INFORMATION
CONVERTER OPERATION
Converter Operation Cycle
The LTC2484 is a low power, delta-sigma analog-to-digital
converter with an easy to use 4-wire serial interface
and automatic differential input current cancellation.
Its operation is made up of three states. The converter
operating cycle begins with the conversion, followed by
the low power sleep state and ends with the data output
(see Figure 1). The 4-wire interface consists of serial data
output (SDO), serial clock (SCK), chip select (CS) and
serial data input (SDI).
Initially, the LTC2484 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
CONVERT
SLEEP
DATA OUTPUT
CONFIGURATION INPUT
2484 F01
TRUE
FALSE
CS = LOW
AND
SCK
Figure 1. LTC2484 State Transition Diagram
CS
SDO
Hi-Z
SIG
DMY
BIT 29
MSB
CONVERSION RESULT
BIT 28
BIT 27
BIT 26
LSB24
BIT 4
BIT 5
BIT 3
BIT 1
BIT 0
BIT 2
BIT 30
SCK
SDI
SLEEP
DATA INPUT/OUTPUT
BIT 31
EOC
EN
DON’T CARE
IM
FOB
FOA
SPD
DON’T CARE
CONVERSION
2484 F02
SUB LSBs
Figure 2. Input/Output Data Timing
While in this sleep state, power consumption is
reduced by two orders of magnitude. The part re-
mains in the sleep state as long as CS is HIGH. The
conversion result is held indenitely in a static shift
register while the converter is in the sleep state.
Once CS is pulled LOW, the device exits the low
power mode and enters the data output state. If CS
is pulled HIGH before the rst rising edge of SCK,
the device returns to the low power sleep mode
and the conversion result is still held in the internal
static shift register. If CS remains LOW after the
rst rising edge of SCK, the device begins output-
ting the conversion result. Taking CS HIGH at this
point will terminate the data input and output state
and start a new conversion. The conversion result
is shifted out of the device through the serial data
output pin (SDO) on the falling edge of the serial
clock (SCK) (see Figure 2). The LTC2484 includes a
serial data input pin (SDI) in which data is latched
by the device on the rising edge of SCK (Figure 2).
The bit stream applied to this pin can be used to
select various features of the LTC2484, including an
on-chip temperature sensor, line frequency rejection
and output data rate. Alternatively, this pin may be
tied to ground and the part will perform conversions
in a default state. In the default state (SDI grounded)
the device simply performs conversions on the user
applied input with simultaneous rejection of 50Hz
and 60Hz line frequencies.
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