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參數(shù)資料
| 型號(hào)： | LTC6946IUFD-2#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 15/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTEGER-N PLL W/VCO 28QFN |
| 軟件下載： | PLLWizard™ PLLWizard™, with .NET 2.0 installer |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘/頻率合成器（RF/IF），分?jǐn)?shù)-N，整數(shù)-N， |
| PLL： | 是 |
| 輸入： | 時(shí)鐘 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 4.91GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.15 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-QFN（4x5） |
| 包裝： | 帶卷 (TR) |
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LTC6946
22
6946fa
APPLICATIONS INFORMATION
4. Select loop filter components CI and CP based on BW
and RZ. A reliable loop can be achieved by using the
following equations for the loop capacitors (in Farads):
CI =
3.5
2 π BW RZ
(8)
CP =
1
7 π BW RZ
(9)
DESIGN AND PROGRAMMING EXAMPLE
This programming example uses the DC1705A with the
LTC6946-3. Assume the following parameters of interest:
fREF = 20MHz at 7dBm into 50Ω
fSTEP = 125kHz
fRF = 2.4GHz
From the Electrical Characteristics table:
fVCO = 3.825GHz to 5.744GHz
KVCO% = 4.0%Hz/V to 6.0%Hz/V
Determining Divider Values
Following the Loop Filter Design algorithm, first deter-
mine all the divider values. Using Equations 2, 3, 4 and 5
calculate the following values:
O = 2
R = 20MHz/(125kHz 2) = 80
fPFD = 250kHz
N = 2 2.4GHz/250kHz = 19200
fVCO = 4.8GHz
Also, from Equation 1 or Table 7 determine B:
B = 8 and BD[3:0] = 0
The next step in the algorithm is to determine the open-
loop bandwidth. BW should be at least 10× smaller than
fPFD. Wider loop bandwidths could have lower integrated
phase noise, depending on the VCO phase noise signature,
while narrower bandwidths will likely have lower spurious
power. Use a factor of 15 for this design example:
BW =
250kHz
15
= 16.7kHz
Loop Filter Component Selection
Now set loop filter resistor, RZ, and charge pump current,
ICP. Because the KVCO varies over the VCO’s frequency
range, using the KVCO geometric mean gives good results.
Using an ICP of 11.2mA, RZ is determined:
K VCO = 4.8 10
9 0.04 0.06 = 235MHz / V
RZ =
2 π 16.7k 19200
11.2m 235M
RZ = 765Ω
Now calculate CI and CP from Equations 7 and 8:
CI =
3.5
2 π 16.7k 765
= 44nF
CP =
1
7 π 16.7k 765
= 3.6nF
Status Output Programming
This example will use the STAT pin to alert the system
whenever the LTC6946 generates a fault condition. Pro-
gram x[5], x[4], x[3], x[1], x[0] = 1 to force the STAT pin
high whenever any of the UNLOCK, ALCHI, ALCLO, THI
or TLO flags asserts:
Reg01 = h3B
Power Register Programming
For correct PLL operation all internal blocks should be
enabled, but PDREFO should be set if the REFO pin is
not being used. OMUTE may remain asserted (or the
MUTE pin held low) until programming is complete. For
PDREFO = 1 and OMUTE = 1:
Reg02 = h0A
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| LTC6946IUFD-3#PBF | 功能描述:IC INTEGER-N PLL W/VCO 28-QFN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| LTC6946IUFD-3#TRPBF | 功能描述:IC INTEGER-N PLL W/VCO 28QFN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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