- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9091 > LTC6946IUFD-2#TRPBF (Linear Technology)IC INTEGER-N PLL W/VCO 28QFN PDF資料下載
參數(shù)資料
| 型號： | LTC6946IUFD-2#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 16/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTEGER-N PLL W/VCO 28QFN |
| 軟件下載： | PLLWizard™ PLLWizard™, with .NET 2.0 installer |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時鐘/頻率合成器（RF/IF），分數(shù)-N，整數(shù)-N， |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 4.91GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.15 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-QFN（4x5） |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁
LTC6946
23
6946fa
APPLICATIONS INFORMATION
Divider Programming
Program registers Reg03 to Reg06 with the previously
determined B, R and N divider values.
Reg03 = h00
Reg04 = h50
Reg05 = h4B
Reg06 = h00
VCO ALC and Calibration Programming
Now that all the divider registers are programmed, and
assuming that the reference frequency is stable at REF±,
calibrate the VCO. Set the ALC options (ALCMON = 1,
ALCCAL = 1) and the lock enable bit (LKEN = 1) at the
same time:
Reg07 = h63
The LTC6946 will now calibrate its VCO. The ALC will only
be active during the calibration cycle, but the ALCHI and
ALCLO status conditions will be monitored.
Reference Input Settings and Output Divider
Programming
From Table 1, FILT = 1 for a 20MHz reference frequency.
Next, convert 7dBm into VP-P. For a CW tone, use the
following equation with R = 50:
VP-P R 10
(dBm – 21)/20
(10)
This gives VP-P = 1.41V, and, according to Table 2, set
BST = 1.
Now program Reg08, assuming maximum RF± output
power (RFO[1:0] = 3 according to Table 9) and OD[2:0] = 2:
Reg08 = hBA
Lock Detect and Charge Pump Current Programming
Next, determine the lock indicator window from fPFD.
From Table 3, LKWIN[1:0] = 3 for a tLWW of 90ns. The
LTC6946 will consider the loop “l(fā)ocked” as long as the
phase coincidence at the PFD is within 8°, as calculated:
phase = 360° tLWW fPFD = 360 90n 250k 8°
LKWIN[1:0] may be set to a smaller value to be more
conservative. However, the inherent phase noise of the
loop could cause false “unlocks” for too small a value.
Choosing the correct LOKCNT depends upon the ratio of
the bandwidth of the loop to the PFD frequency (BW/fPFD).
Smaller ratios dictate larger LOKCNT values. A LOKCNT
value of 128 will work for our ratio of 1/15. From Table 4,
LKCNT[1:0] = 1 for 128 counts.
Using Table 5 with the previously selected ICP of 11.2mA,
gives CP[3:0] = 11 (hB). This is enough information to
program Reg09:
Reg09 = hDB
Charge Pump Function Programming
This example uses the additional voltage clamp features to
allow us to monitor fault conditions by setting CPCHI = 1
and CPCLO = 1. If something occurs and the system can
no longer lock to its intended frequency, the charge pump
output will move toward either GND or VCP+,therebysetting
either the TLO or THI status flags, respectively. Disable all
the other charge pump functions (CPMID, CPINV, CPRST,
CPUP and CPDN) to allow the loop to lock:
Reg0A = hC0
The loop should now lock. Now unmute the output by
setting OMUTE = 0 (assumes the MUTE pin is high):
Reg02 = h08
REFERENCE SOURCE CONSIDERATIONS
A high quality signal must be applied to the REF± inputs as
they provide the frequency reference to the entire PLL. As
mentioned previously, to achieve the part’s in-band phase
noise performance, apply a CW signal of at least 6dBm
into 50Ω, or a square wave of at least 0.5VP-P with slew
rate of at least 40V/μs.
The LTC6946 may be driven single ended to CMOS levels
(greater than 2.7VP-P ). Apply the reference signal directly
without a DC-blocking capacitor at REF+, and bypass
REF– to GND with a 47pF capacitor. The BST bit must also
be set to “0”, according to guidelines given in Table 2.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC6946IUFD-1#TRPBF | IC INTEGER-N PLL W/VCO 28QFN |
| X9410WV24IZ | IC XDCP DUAL 64-TAP 10K 24-TSSOP |
| X9410WV24IT1 | IC XDCP DUAL 64-TAP 10K 24-TSSOP |
| M83723/78W20397 | CONN PLUG 39POS STRAIGHT W/PINS |
| ADF4106SCPZ-EP-R7 | IC PLL FREQ SYNTHESIZER 20LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC6946IUFD-3#PBF | 功能描述:IC INTEGER-N PLL W/VCO 28-QFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| LTC6946IUFD-3#TRPBF | 功能描述:IC INTEGER-N PLL W/VCO 28QFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| LTC6946-x | 制造商:LINER 制造商全稱:Linear Technology 功能描述:16-Bit, 20Msps Low Noise Dual ADC |
| LTC694C | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Microprocessor Supervisory Circuits |
| LTC694C-3.3 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:3.3V Microprocessor Supervisory Circuits |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。