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參數(shù)資料
| 型號： | LXT332 |
| 廠商： | Digital Data Communications GmbH |
| 英文描述： | 3941 |
| 中文描述： | 雙T1/E1線路接口單元與水晶無衰減 |
| 文件頁數(shù)： | 5/32頁 |
| 文件大?。?/td> | 777K |
| 代理商： | LXT332 |
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TPOS0
(Bipolar)
TNEG0
(Bipolar)
RNEG0
(Bipolar)
DI
DI
Transmit Positive and Negative Data - Port 0.
In the Bipolar I/O mode,
these pins are the positive and negative sides of a bipolar input pair for port
0. Data to be transmitted onto the twisted-pair line is input at these pins.
However, when the TRSTE pin is clocked by MCLK, the LXT332 switches
to a unipolar mode. Table 2 describes Unipolar mode pin functions.
Receive Positive and Negative Data - Port 0.
In the Bipolar I/O mode,
these pins are the data outputs from port 0. A signal on RNEG corresponds
to receipt of a negative pulse on RTIP/RRING. A signal on RPOS corre-
sponds to receipt of a positive pulse on RTIP/RRING. RNEG/RPOS outputs
are Non-Return-to-Zero (NRZ). In Host mode, CLKE determines the clock
edge at which these outputs are stable and valid.
Receive Clock - Port 0.
This clock is recovered from the input signal.
Under Loss of Signal (LOS) conditions, this output is derived from MCLK.
Serial Clock.
The Serial Clock shifts data into or out from the serial inter-
face register of the selected port.
Provides Violation insert, High Frequency Clock, or QRSS generation/detec-
tion functions for Port 0. Pin operation is determined by the VCQE pin.
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RPOS0
(Bipolar)
DO
DO
ì
RCLK0
DO
SCLK
DI
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VCQ0
DI/O
Violation Insertion Function.
When the
V
iolation insertion function is
enabled, this pin is sampled on the falling edge of TCLK to control bipolar
violation (BPV) insertion. If High, a BPV is inserted at the next available
mark transmitted from port 0. A Low-to-High transition is required for each
subsequent violation insertion. (B8ZS and HDB3 zero suppression codes are
not violated.)
Clock Function.
When the
C
lock function is enabled, this pin outputs a
High Frequency Clock (12.352 MHz for T1, 16.384 MHz for E1) tied to the
jitter attenuated clock of port 0. If no JA clock is available, HFC is locked to
the 8x receive timing recovery clock.
Quasi Random Signal Source (QRSS) Function.
When the QRSS function
is enabled, a High on this pin enables the QRSS detection circuit and causes
the LXT332 to transmit the QRSS pattern onto the twisted-pair line from
port 0. For error-free QRSS transmission, TPOS0 must be held Low. To
insert errors into the pattern, TPOS must transition from Low to High (TPOS
is sampled on the falling edge of MCLK). A Low-to-High transition is
required for each subsequent violation insertion. (B8ZS and HDB3 zero
suppression codes are not violated.)
Interrupt Outputs.
The interrupt outputs go Low to flag the host processor
that the respective port has changed state. INT0 and INT1 are open drain
outputs. Each must be tied to VCC through a resistor.
Master Clock.
The master clock (1.544 MHz for T1, 2.048 MHz for E1)
input must be independent, free-running, continuously active and jitter free
for receiver operation. Since the transceivers derive their RCLK timing from
the MCLK input on Loss of Signal (LOS), MCLK cannot be derived from
RCLK.
Ground.
Ground return for power supply VCC.
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INT1
INT0
DO
DO
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MCLK
DI
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GND
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