參數(shù)資料
型號(hào)： LXT332
廠商： Digital Data Communications GmbH
英文描述： 3941
中文描述： 雙T1/E1線路接口單元與水晶無(wú)衰減
文件頁(yè)數(shù)： 9/32頁(yè)
文件大?。?/td> 777K
代理商： LXT332
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RCLK0
DO
Receive Clock - Port 0.
This clock is recovered from the input signal. Under
Loss of Signal (LOS) conditions, this output is derived from MCLK.
Transmit All Ones Enable - Port 0.
When TAOS is High and RLOOP is
Low, the TPOS/TNEG or TDATA input is ignored and port 0 transmits a
stream of ones at the TCLK frequency. If TCLK is not provided, the MCLK
input is used as the transmit reference.
Line Length Equalizer Inputs - Port 0.
This pins determine the shape and
amplitude of the transmit pulse.
TAOS0
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LEN20
LEN10
LEN00
MCLK
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Master Clock.
The master clock (1.544 MHz for T1, 2.048 MHz for E1) input
must be independent, free-running, continuously active and jitter free for
receiver operation. Since the transceivers derive their RCLK timing from the
MCLK input on Loss of Signal (LOS), MCLK cannot be derived from RCLK.
Ground.
Ground return for power supply VCC.
Transmit Tip and Ring - Port 0.
The tip and ring pins for each port are dif-
ferential driver outputs designed to drive a 35 - 200
load. Line matching
resistors and transformers can be selected to give the desired pulse height. See
Figures 13 through 15.
Ground.
Ground return for power supply TVCC0.
+ 5 volt
power supply input for the port 0 transmit driver. TVCC0 must not
vary from TVCC1 or VCC by more than ± 0.3 V.
Driver Fail Monitor.
This signal goes High to indicate a driver output short
in one or both ports.
Remote Loopback Enable - Port 0.
When RLOOP = 1, the port 0 clock and
data inputs from the framer are ignored and the data received from the twisted-
pair line is transmitted back onto the line at the RCLK frequency.
(LLOOP0
must be Low for RLOOP0 to occur.)
Loss of Signal - Port 0.
LOS goes High when 175 consecutive spaces have
been detected. LOS returns Low when the received signal reaches a mark den-
sity of 12.5% (determined by receipt of four marks with a sliding 32-bit period
with no more than 15 consecutive zeros). Received marks are output on
RPOS/RNEG or RDATA even when LOS is High.
Receive Tip and Ring - Port 0.
RTIP and RRING comprise the receive line
interface. This input pair should be connected to the line through a center-
tapped 1:2 transformer.
Local Loopback Enable - Port 0.
When LLOOP is High, the RTIP/RRING
inputs from the port 0 line are disconnected and the transmit data inputs are
routed back into the receive inputs (through JA if enabled).
(RLOOP0 must
be Low for LLOOP0 to occur.)
Receive Tip and Ring - Port 1.
RTIP and RRING comprise the receive line
interface. This input pair should be connected to the line through a center-
tapped 1:2 transformer.
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GND
TTIP0
TRING0
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TGND0
TVCC0
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DFM
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RLOOP0
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LOS0
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RTIP0
RRING0
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LLOOP0
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RRING1
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