參數(shù)資料
型號(hào)： M13S2561616A-5TG
廠商： ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類： DRAM
英文描述： 4M x 16 Bit x 4 Banks Double Data Rate SDRAM
中文描述： 16M X 16 DDR DRAM, 0.75 ns, PDSO66
封裝： 0.400 X 875 INCH, 0.65 MM PITCH, LEAD FREE, TSOP2-66
文件頁(yè)數(shù)： 10/48頁(yè)
文件大小： 1232K
代理商： M13S2561616A-5TG
ES MT
M13S2561616A
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.3 10/48
Basic Functionality
Power-Up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.)
-
Apply VDD before or at the same time as VDDQ.
-
Apply VDDQ before or at the same time as V
TT
& V
REF
).
2. Start clock and maintain stable condition for a minimun of 200us.
3. The minimun of 200us after stable power and clock (CLK, CLK ), apply NOP & take CKE high.
4. Issue precharge commands for all banks of the device.
*1 5. ssue EMRS to enable DLL. (To issue “DLL Enable” command, provide “Low” to A0, “High” to BA0 and “Low” to all of the
rest address pins, A1~A12 and BA1)
*1 6. Issue a mode register set command for “DLL reset”. The additional 200 cycles of clock input is required to lock the DLL.
(To issue DLL reset command, provide “High” to A8 and “Low” to BA0)
*2 7. Issue precharge commands for all banks of the device.
8. Issue 2 or more auto-refresh commands.
9. Issue a mode register set command with low to A8 to initialize device operation.
*1 Every “DLL enable” command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it, the additional
200 cycles of clock input is required to lock the DLL after enabling DLL.
*2 Sequence of 6 & 7 is regardless of the order.
C L K
C L K
C o m m a n d
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
t
R P
p recharg e
A l l B a nk s
EMRS
M R S
D l l R e s e t
t
R P
precha rg e
A l l B a nk s
1s t A ut o
Re f re s h
t
R F C
2nd A ut o
Re f re s h
t
R F C
Mode
Register Set
A n y
C ommand
m in . 20 0 Cy c l e
Power up & Initialization Sequence
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M13S2561616A-5TIG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:4M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S2561616A-6BG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:4M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S2561616A-6BIG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:4M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S2561616A-6TG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:4M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S2561616A-6TIG 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:4M x 16 Bit x 4 Banks Double Data Rate SDRAM
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