參數(shù)資料
型號: M13S256328A
廠商: Elite Semiconductor Memory Technology Inc.
英文描述: 2M x 32 Bit x 4 Banks Double Data Rate SDRAM
中文描述: 200萬× 32位× 4個銀行雙倍數(shù)據(jù)速率SDRAM
文件頁數(shù): 1/47頁
文件大?。?/td> 807K
代理商: M13S256328A
ES MT
M13S256328A
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.2 1/47
DDR SDRAM
2M x 32 Bit x 4 Banks
Double Data Rate SDRAM
Features
z
JEDEC Standard
z
Internal pipelined double-data-rate architecture, two data access per clock cycle
z
Bi-directional data strobe (DQS)
z
On-chip DLL
z
Differential clock inputs (CLK and CLK )
z
DLL aligns DQ and DQS transition with CLK transition
z
Quad bank operation
z
CAS Latency : 2; 2.5; 3
z
Burst Type : Sequential and Interleave
z
Burst Length : 2, 4, 8, full page
z
Full page burst length for sequential burst type only
z
Start address of the full page burst should be even
z
All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
z
Data I/O transitions on both edges of data strobe (DQS)
z
DQS is edge-aligned with data for reads; center-aligned with data for WRITE
z
Data mask (DM) for write masking only
z
V
DD
= 2.3V ~ 2.7V, V
DDQ
= 2.3V ~ 2.7V
z
Auto & Self refresh
z
64ms refresh period (8K cycle)
z
SSTL-2 I/O interface
z
144Ball FBGA package
Operating Frequencies :
PRODUCT NO.
MAX FREQ
VDD
PACKAGE
COMMENTS
M13S256328A -5BG
200MHz
2.5V
144 Ball FBGA
Pb-free
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