參數(shù)資料
型號(hào)： M24256-BFMB6TG/K
廠商： STMICROELECTRONICS
元件分類： PROM
英文描述： 32K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8
封裝： 2 X 3 MM, ROHS COMPLIANT, UFDFPN-8
文件頁(yè)數(shù)： 21/42頁(yè)
文件大?。?/td> 501K
代理商： M24256-BFMB6TG/K
DC and AC parameters
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Doc ID 6757 Rev 21
Table 16.
400 kHz AC characteristics
Test conditions specified in Table 8, Table 9, Table 10 and Table 11
Symbol
Alt.
Parameter
Min.(1)
1.
All values are referred to VIL(max) and VIH(min).
Max.(1)
Unit
fC
fSCL
Clock frequency
400
kHz
tCHCL
tHIGH
Clock pulse width high
600
ns
tCLCH
tLOW
Clock pulse width low
1300
ns
tQL1QL2
(2)
2.
Characterized only, not tested in production.
tF
SDA (out) fall time
20(3)
3.
With CL = 10 pF.
120
ns
tXH1XH2
tR
Input signal rise time
(4)
4.
There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
IC specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
fC < 400 kHz.
ns
tXL1XL2
tF
Input signal fall time
ns
tDXCX
tSU:DAT
Data in set up time
100
ns
tCLDX
tHD:DAT
Data in hold time
0
ns
tCLQX
tDH
Data out hold time
100(5)
5.
The new M24xxx-W, M24xxx-R, and M24xxx-BF devices (identified by the process letter K) offer
tCLQX = 100 ns (min) and tCLQV = 100 ns (min), while the current devices (process letter A) offer
tCLQX = 200 ns (min) and tCLQV = 200 ns (min). Both series offer a safe margin compared to the I
2C
specification which recommends tCLQV = 0 ns (min).
ns
tCLQV
(6)(7)
6.
To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
7.
tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or
0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 6.
tAA
Clock low to next data valid (access time)
100(5)
900
ns
tCHDL
tSU:STA
Start condition setup time
600
ns
tDLCL
tHD:STA
Start condition hold time
600
ns
tCHDH
tSU:STO Stop condition set up time
600
ns
tDHDL
tBUF
Time between Stop condition and next Start
condition
1300
ns
tW
tWR
Write time
5
ms
tNS
Pulse width ignored (input filter on SCL and
SDA) - single glitch
80(8)
8.
The current M24xxx devices (identified by the Process letter A) offer tNS=100 ns (min), the new M24256-
BR and M24256-DR device (identified by the process letter K) offer tNS=80 ns (min). Both products offer a
safe margin compared to the 50 ns minimum value recommended by the I2C specification.
ns
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M24256-BFMC6TG 功能描述:電可擦除可編程只讀存儲(chǔ)器 256kB Serial I2C 3-Chip Enable 1 MHz RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8
M24256-BHR 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:512 Kbit and 256 Kbit serial IC bus EEPROM with three Chip Enable lines
M24256-BHRDW6TP 功能描述:電可擦除可編程只讀存儲(chǔ)器 512 Kbit/256 Kbit serial 電可擦除可編程只讀存儲(chǔ)器 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8
M24256-BHRMN6P 功能描述:電可擦除可編程只讀存儲(chǔ)器 512Kbit and 256Kbit bus 電可擦除可編程只讀存儲(chǔ)器 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8
M24256-BHRMN6TP 功能描述:電可擦除可編程只讀存儲(chǔ)器 513 Kbit/256 Kbit serial 電可擦除可編程只讀存儲(chǔ)器 RoHS:否 制造商:Atmel 存儲(chǔ)容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時(shí)鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8
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