參數(shù)資料
型號(hào): M25P40-VMN6TP
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: 4 Mbit Uniform Sector, Serial Flash Memory
中文描述: 4兆位統(tǒng)一部門,串行閃存
文件頁(yè)數(shù): 27/40頁(yè)
文件大小: 232K
代理商: M25P40-VMN6TP
27/40
M25P40
Figure 20. Power-up Timing
Table 7. Power-Up Timing and V
WI
Threshold
Symbol
Note: 1. These parameters are characterized only.
INITIAL DELIVERY STATE
The device is delivered with the memory array
erased: all bits are set to 1 (each byte contains
FFh). The Status Register contains 00h (all Status
Register bits are 0).
Parameter
Min.
Max.
Unit
t
VSL1
V
CC
(min) to S low
10
μs
t
PUW1
Time delay to Write instruction
1
10
ms
V
WI1
Write Inhibit Voltage
1
2
V
VCC
AI04009C
VCC(min)
VWI
Reset State
of the
Device
Chip Selection Not Allowed
Program, Erase and Write Commands are Rejected by the Device
tVSL
tPUW
time
Read Access allowed
Device fully
accessible
VCC(max)
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