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參數(shù)資料
| 型號： | M25PE16-VMW6TG |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 4 Mbit Uniform Sector, Serial Flash Memory |
| 中文描述： | 4兆位統(tǒng)一部門，串行閃存 |
| 文件頁數(shù)： | 25/56頁 |
| 文件大?。?/td> | 334K |
| 代理商： | M25PE16-VMW6TG |
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M25PE16
Instructions
25/56
6.4
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Program, Erase or Write cycle is in
progress. When one of these cycles is in progress, it is recommended to check the Write In
Progress (WIP) bit before sending a new instruction to the device. It is also possible to read
the Status Register continuously, as shown in
Figure 9
.
The status bits of the Status Register are as follows:
6.4.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write, Program
or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is
in progress.
6.4.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write, Program or Erase instruction is accepted.
6.4.3
BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to
be software protected against Program and Erase instructions. These bits are written with
the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2,
BP1, BP0) bits is set to 1, the relevant memory area (as defined in
Table 3
) becomes
protected against Page Program (PP), Sector Erase (SE) and SubSector Erase (SSE)
instructions. The Block Protect (BP2, BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if,
and only if:
all Block Protect (BP2, BP1, BP0) bits are 0
the Lock Register protection bits are not all set (‘1’)
●
●
6.4.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. When the Status Register Write Disable (SRWD) bit is set to 1, and Write
Protect (W) is driven Low, the non-volatile bits of the Status Register (SRWD, BP2, BP1,
BP0) become read-only bits. In such a state, as the Write Status Register (WRSR)
instruction is no longer accepted for execution, the definition of the size of the Write
Protected area
cannot
be further modified.
Table 7.
Status Register format
(1)
(2)
1.
WEL (Write Enable Latch) and WIP ((Write In Program) are volatile read-only bits (WEL is set and reset by
specific instructions; WIP is automatically set and reset by the internal logic of the device).
2.
SRWD = Status Register Write Protect bit; BP0, BP1, BP2 = Block Protect Bits.
b7
b0
SRWD
0
0
BP2
BP1
BP0
WEL
WIP
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M25PE16-VMW6TP | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE40 | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE40VMN6G | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE40VMN6P | 4 Mbit Uniform Sector, Serial Flash Memory |
| M25PE40VMN6TG | 4 Mbit Uniform Sector, Serial Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M25PE16-VMW6TP | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:16-Mbit, page-erasable serial flash memory with byte-alterability, 75 MHz SPI bus, standard pinout |
| M25PE20 | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:1 and 2 Mbit, page-erasable serial Flash memories with byte alterability, 75 MHz SPI bus, standard pinout |
| M25PE20_07 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 and 2 Mbit, low voltage, Page-Erasable Serial Flash memories with Byte-Alterability, 50 MHz SPI bus, standard pinout |
| M25PE20-V6D11 | 制造商:Micron Technology Inc 功能描述:SERIAL NOR 制造商:Micron Technology Inc 功能描述:SERIAL NOR - Gel-pak, waffle pack, wafer, diced wafer on film |
| M25PE20-VMN6G | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 and 2 Mbit, low voltage, Page-Erasable Serial Flash memories with Byte-Alterability, 50 MHz SPI bus, standard pinout |
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