參數(shù)資料
型號(hào)： M25PE16-VMW6TG
廠商： 意法半導(dǎo)體
元件分類(lèi)： DRAM
英文描述： 4 Mbit Uniform Sector, Serial Flash Memory
中文描述： 4兆位統(tǒng)一部門(mén)，串行閃存
文件頁(yè)數(shù)： 31/56頁(yè)
文件大?。?/td> 334K
代理商： M25PE16-VMW6TG
M25PE16
Instructions
31/56
6.8
Read Lock Register (RDLR)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Lock Register (RDLR) instruction is followed by a 3-Byte address (A23-A0) pointing to any
location inside the concerned sector. Each address bit is latched-in during the rising edge of
Serial Clock (C). Then the value of the Lock Register is shifted out on Serial Data Output
(Q), each bit being shifted out, at a maximum frequency f
C
, during the falling edge of Serial
Clock (C).
The instruction sequence is shown in
Figure 13
.
The Read Lock Register (RDLR) instruction is terminated by driving Chip Select (S) High at
any time during data output.
Any Read Lock Register (RDLR) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Table 9.
Figure 13.
Read Lock Register (RDLR) instruction sequence
and data-out sequence
Lock Register out
Bit
Bit Name
Value
Function
b7-b2
Reserved
b1
Sector Lock Down
‘1’
The Write Lock and Lock Down Bits cannot be changed.
Once a ‘1’ is written to the Lock Down Bit it cannot be cleared
to ‘0’, except by a Reset or power-up.
‘0’
The Write Lock and Lock Down Bits can be changed by
writing new values to them. (Default value).
b0
Sector Write Lock
‘1’
Write, Program and Erase operations in this sector will not be
executed. The memory contents will not be changed.
‘0’
Write, Program and Erase operations in this sector are
executed and will modify the sector contents. (Default value).
C
D
AI10783
S
Q
23
2
1
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35
22 21
3
2
1
0
36 37 38
7
6
5
4
3
1
0
High Impedance
Lock Register Out
Instruction
24-Bit Address
0
MSB
MSB
2
39
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