參數(shù)資料
型號: M25PE16-VMW6TP
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: 4 Mbit Uniform Sector, Serial Flash Memory
中文描述: 4兆位統(tǒng)一部門,串行閃存
文件頁數(shù): 37/56頁
文件大?。?/td> 334K
代理商: M25PE16-VMW6TP
M25PE16
Instructions
37/56
6.12
Page Erase (PE)
The Page Erase (PE) instruction sets to 1 (FFh) all bits inside the chosen page. Before it can
be accepted, a Write Enable (WREN) instruction must previously have been executed. After
the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable
Latch (WEL).
The Page Erase (PE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address Bytes on Serial Data Input (D). Any address inside the
Page is a valid address for the Page Erase (PE) instruction. Chip Select (S) must be driven
Low for the entire duration of the sequence.
The instruction sequence is shown in
Figure 17
.
Chip Select (S) must be driven High after the eighth bit of the last address Byte has been
latched in, otherwise the Page Erase (PE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed Page Erase cycle (whose duration is t
PE
) is initiated.
While the Page Erase cycle is in progress, the Status Register may be read to check the
value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-
timed Page Erase cycle, and is 0 when it is completed. At some unspecified time before the
cycle is complete, the Write Enable Latch (WEL) bit is reset.
A Page Erase (PE) instruction applied to a page that is Hardware or software Protected is
not executed.
Any Page Erase (PE) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
If Reset (RESET) is driven Low while a Page Erase (PE) cycle is in progress, the Page
Erase cycle is interrupted and the programmed data may be corrupted (see
Table 12:
Device status after a RESET Low pulse
). On RESET going Low, the device enters the Reset
mode and a time of t
RHSL
is then required before the device can be re-selected by driving
Chip Select (S) Low. For the value of t
RHSL
see
Table 20: Timings after a RESET Low pulse
in
Section 11: DC and AC parameters
.
Figure 17.
Page Erase (PE)
instruction sequence
1.
Address bits A23 to A21 are Don’t Care.
24 Bit Address
C
D
AI04046
S
2
1
3
4
5
6
7
8
9
29 30 31
Instruction
0
23 22
2
0
1
MSB
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