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參數(shù)資料
| 型號： | M25PE80-VMW6TP |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | DRAM |
| 英文描述： | 4 Mbit Uniform Sector, Serial Flash Memory |
| 中文描述： | 4兆位統(tǒng)一部門，串行閃存 |
| 文件頁數(shù)： | 35/43頁 |
| 文件大?。?/td> | 599K |
| 代理商： | M25PE80-VMW6TP |
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M25PE80
Table 16. AC Characteristics
Note: 1. t
CH
+ t
CL
must be greater than or equal to 1/ f
C
2. Value guaranteed by characterization, not 100% tested in production.
3. When using PP and PW instructions to update consecutive Bytes, optimized timings are obtained with one sequence including all
the Bytes versus several sequences of only a few Bytes.
Test conditions specified in
Table 12.
and
Table 13.
Symbol
Alt.
Parameter
Min.
Typ.
Max.
Unit
f
C
f
C
Clock Frequency for the following
instructions: FAST_READ, RDLR, PW,
PP, WRLR, PE, SE, DP, RDP, WREN,
WRDI, RDSR
D.C.
50
MHz
f
R
Clock Frequency for READ
instructions
D.C.
20
MHz
t
CH (1)
t
CLH
Clock High Time
9
ns
t
CL (1)
t
CLL
Clock Low Time
9
ns
Clock Slew Rate
2
(peak to peak)
0.1
V/ns
t
SLCH
t
CSS
S Active Setup Time (relative to C)
9
ns
t
CHSL
S Not Active Hold Time (relative to C)
9
ns
t
DVCH
t
DSU
Data In Setup Time
2
ns
t
CHDX
t
DH
Data In Hold Time
5
ns
t
CHSH
S Active Hold Time (relative to C)
9
ns
t
SHCH
S Not Active Setup Time (relative to C)
9
ns
t
SHSL
t
CSH
S Deselect Time
100
ns
t
SHQZ (2)
t
DIS
Output Disable Time
8
ns
t
CLQV
t
V
Clock Low to Output Valid
8
ns
t
CLQX
t
HO
Output Hold Time
0
ns
t
THSL
Top Sector Lock Setup Time
50
ns
t
SHTL
Top Sector Lock Hold Time
100
ns
t
DP (2)
S to Deep Power-down
3
μ
s
t
RDP (2)
S High to Standby Mode
30
μ
s
t
PW (3)
Page Write Cycle Time (256 Bytes)
11
25
ms
Page Write Cycle Time (n Bytes)
10.2 +
n * 0.8/256
t
PP (3)
Page Program Cycle Time (256 Bytes)
1.2
5
ms
Page Program Cycle Time (n Bytes)
0.4 +
n * 0.8/256
t
PE
Page Erase Cycle Time
10
20
ms
t
SE
Sector Erase Cycle Time
1
5
s
t
BE
Bulk Erase Cycle Time
16
60
s
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