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參數資料
| 型號： | M29W800FB9N3F |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 512K X 16 FLASH 3V PROM, 90 ns, PDSO48 |
| 封裝： | 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP-48 |
| 文件頁數： | 46/49頁 |
| 文件大?。?/td> | 936K |
| 代理商： | M29W800FB9N3F |
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Description
M29W800FT, M29W800FB
1
Description
The M29W800FT/B is an 8-Mbit (1 Mbit × 8 or 512 Kbit × 16) non-volatile memory that can
be read, erased and reprogrammed. These operations can be performed using a single low
voltage (2.7 V to 3.6 V) supply. On power-up the memory defaults to its read mode where it
can be read in the same way as a ROM or EPROM.
The memory is divided into blocks that can be erased independently so it is possible to
preserve valid data while old data is erased. Each block can be protected independently to
prevent accidental Program or Erase commands from modifying the memory. Program and
Erase commands are written to the command interface of the memory. An on-chip
program/erase controller simplifies the process of programming or erasing the memory by
taking care of all of the special operations that are required to update the memory contents.
The end of a program or erase operation can be detected and any error conditions
identified. The command set required to control the memory is consistent with JEDEC
standards.
The blocks in the memory are asymmetrically arranged, see Figure 3: Block addresses (× 8)
and Figure 4: Block addresses (× 16). The first or last 64 Kbytes have been divided into four
additional blocks. The 16-Kbyte boot block can be used for small initialization code to start
the microprocessor, the two 8-Kbyte parameter blocks can be used for parameter storage
and the remaining 32-Kbyte is a small main block where the application may be stored.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the
memory. They allow simple connection to most microprocessors, often without additional
logic.
The memory is offered in TSOP48 (12 × 20 mm) and TFBGA48 6 × 8 mm (0.8 mm pitch)
packages. The memory is supplied with all the bits erased (set to ’1’).
Figure 1.
Logic diagram
AI13852
19
A0-A18
W
DQ0-DQ14
VCC
M29W800FT
M29W800FB
E
VSS
15
G
RP
DQ15A–1
RB
BYTE
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