參數(shù)資料
型號(hào): M30220FCGP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù): 22/161頁
文件大?。?/td> 0K
代理商: M30220FCGP
110
EPSON
S1C88832/88862 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (SVD Circuit)
Table 5.13.2.2 Supply voltage detection results
The SVD circuit starts operation in synchroniza-
tion with the internal 2,048 Hz signal and
performs one sampling in 16 clock cycles.
The sampling is done continuously without
setting the standby time and the result is
latched to SVD0–SVD3 in every 16 clock cycles.
Cancellation of continuous sampling is done by
writing "0" to SVDON. The SVD circuit main-
tains ON status until completion of sampling
and then goes OFF.
After writing "0" to SVDON, SVDON reads "1"
until the SVD circuit actually goes OFF.
Figure 5.13.2.1 shows the timing chart of the
continuous sampling.
(2) 1/4 Hz auto-sampling mode
This mode is selected when "0" is written to
SVDON and "1" is written to SVDSP. In this
case, supply voltage sampling is done in every 4
seconds.
The sampling time is 7.8 msec as in continuous
sampling, and the result in SVD0–SVD3 is
updated every 4 seconds.
Cancellation of 1/4 Hz auto-sampling is done
by writing "0" to SVDSP. If the SVD circuit is
sampling, SVD circuit waits until completion
and then turns OFF. In addition, "1" is read from
SVDON while the SVD circuit is sampling.
Figure 5.13.2.2 shows the timing chart of the 1/4
Hz auto-sampling.
s Timing of sampling
Next, we will explain the timing for two operation
modes.
(1) Continuous sampling mode
This mode is selected when "1" is written to
SVDON and sampling of the supply voltage is
done continuously in 7.8 msec cycles.
Fig. 5.13.2.1 Timing chart of continuous sampling
SVD0–SVD3
1 Hz
SVDSP(W)
SVDON(R)
Sampling (7.8 msec)
Standby status
4 sec
Fig. 5.13.2.2 Timing chart of 1/4 Hz auto-sampling
SVD3
SVD0
Detection level
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1
Level 0
SVD1
1
0
1
0
1
0
1
0
SVD2
1
0
1
0
SVD0–SVD3
2,048 Hz
SVDON(W)
Latch
Sampling (7.8 msec)
SVDON(R)
(0)
(1)
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