參數(shù)資料
型號(hào)： M30220FCGP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù)： 91/161頁
文件大?。?/td> 0K
代理商： M30220FCGP
Interrupt
Mitsubishi microcomputers
M30220 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
35
Figure 1.10.3. Interrupt control registers
Symbol
Address
When reset
INTiIC(i=0 to 2)
005D16 to 005F16
XX00X0002
(i=3)
004416
XX00X0002
TAiIC/INTjIC(i=3, 4)
005816, 005916
XX00X0002
(j=4, 5)
005816, 005916
XX00X0002
Bit name
Function
Bit symbol
W
R
b7
b6
b5
b4
b3
b2
b1
b0
ILVL0
IR
POL
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be indeterminate.
Interrupt priority level
select bit
Interrupt request bit
Polarity select bit
Reserved bit
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge
1 : Selects rising edge
Must always be set to “0”
ILVL1
ILVL2
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the
interrupt request for that register. For details, see the precautions for interrupts.
(Note 1)
Interrupt control register (Note2)
b7
b6
b5
b4
b3
b2
b1
b0
Bit name
Function
Bit symbol
W
R
Symbol
Address
When reset
TBiIC(i=3 to 5)
004516 to 004716
XXXXX0002
TAiIC(i=6, 7)
004816, 004916
XXXXX0002
TA5IC/BCNIC
004A16
XXXXX0002
DMiIC(i=0, 1)
004B16, 004C16
XXXXX0002
KUPIC
004D16
XXXXX0002
ADIC
004E16
XXXXX0002
SiTIC(i=0 to 2)
005116, 005316, 004F16
XXXXX0002
SiRIC(i=0 to 2)
005216, 005416, 005016
XXXXX0002
TAiIC(i=0 to 2)
005516 to 005716
XXXXX0002
TBiIC(i=0 to 2)
005A16 to 005C16
XXXXX0002
ILVL0
IR
Interrupt priority level
select bit
Interrupt request bit
0 : Interrupt not requested
1 : Interrupt requested
ILVL1
ILVL2
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be indeterminate.
(Note 1)
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the
interrupt request for that register. For details, see the precautions for interrupts.
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
b2 b1 b0
0
Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selec-
tion bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is
indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit
are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the
IPL are located in the flag register (FLG).
Figure 1.10.3 shows the memory map of the interrupt control registers.
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